Lines Matching defs:dyn
63 const struct vk_dynamic_graphics_state *dyn =
68 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_IA_PRIMITIVE_TOPOLOGY) ||
69 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_CULL_MODE) ||
70 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_FRONT_FACE) ||
71 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_ENABLE) ||
72 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_FACTORS) ||
73 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_LINE_WIDTH)) {
79 dyn->ia.primitive_topology);
90 .LineWidth = dyn->rs.line.width,
92 .CullMode = genX(vk_to_intel_cullmode)[dyn->rs.cull_mode],
93 .FrontWinding = genX(vk_to_intel_front_face)[dyn->rs.front_face],
95 .GlobalDepthOffsetEnableSolid = dyn->rs.depth_bias.enable,
96 .GlobalDepthOffsetEnableWireframe = dyn->rs.depth_bias.enable,
97 .GlobalDepthOffsetEnablePoint = dyn->rs.depth_bias.enable,
98 .GlobalDepthOffsetConstant = dyn->rs.depth_bias.constant,
99 .GlobalDepthOffsetScale = dyn->rs.depth_bias.slope,
100 .GlobalDepthOffsetClamp = dyn->rs.depth_bias.clamp,
107 if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_REFERENCE) ||
108 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_BLEND_CONSTANTS)) {
114 .BlendConstantColorRed = dyn->cb.blend_constants[0],
115 .BlendConstantColorGreen = dyn->cb.blend_constants[1],
116 .BlendConstantColorBlue = dyn->cb.blend_constants[2],
117 .BlendConstantColorAlpha = dyn->cb.blend_constants[3],
118 .StencilReferenceValue = dyn->ds.stencil.front.reference & 0xff,
119 .BackfaceStencilReferenceValue = dyn->ds.stencil.back.reference & 0xff,
128 if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_LINE_STIPPLE)) {
130 ls.LineStipplePattern = dyn->rs.line.stipple.pattern;
132 1.0f / MAX2(1, dyn->rs.line.stipple.factor);
133 ls.LineStippleRepeatCount = dyn->rs.line.stipple.factor;
139 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_DEPTH_TEST_ENABLE) ||
140 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_DEPTH_WRITE_ENABLE) ||
141 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_DEPTH_COMPARE_OP) ||
142 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_TEST_ENABLE) ||
143 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_OP) ||
144 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_COMPARE_MASK) ||
145 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_WRITE_MASK)) {
154 struct vk_depth_stencil_state opt_ds = dyn->ds;
195 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_IA_PRIMITIVE_RESTART_ENABLE))) {
201 vf.IndexedDrawCutIndexEnable = dyn->ia.primitive_restart_enable;
208 ib.CutIndexEnable = dyn->ia.primitive_restart_enable;
226 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_IA_PRIMITIVE_TOPOLOGY) ||
227 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES)) {
230 dyn->ia.primitive_topology);
249 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_SAMPLE_LOCATIONS)) {
251 const struct vk_sample_locations_state *sl = dyn->ms.sample_locations;
257 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP) ||
258 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES)) {
259 const uint8_t color_writes = dyn->cb.color_write_enables;
287 .LogicOpFunction = genX(vk_to_intel_logic_op)[dyn->cb.logic_op],