Lines Matching defs:cfg
171 const struct intel_l3_config *cfg = intel_get_default_l3_config(&device->info);
172 genX(emit_l3_config)(batch, device, cfg);
173 device->l3_config = cfg;
593 const struct intel_l3_config *cfg)
608 if (cfg == NULL) {
616 l3cr.SLMEnable = cfg->n[INTEL_L3P_SLM];
626 assert(cfg->n[INTEL_L3P_IS] == 0);
627 assert(cfg->n[INTEL_L3P_C] == 0);
628 assert(cfg->n[INTEL_L3P_T] == 0);
629 l3cr.URBAllocation = cfg->n[INTEL_L3P_URB];
630 l3cr.ROAllocation = cfg->n[INTEL_L3P_RO];
631 l3cr.DCAllocation = cfg->n[INTEL_L3P_DC];
632 l3cr.AllAllocation = cfg->n[INTEL_L3P_ALL];
638 const bool has_dc = cfg->n[INTEL_L3P_DC] || cfg->n[INTEL_L3P_ALL];
639 const bool has_is = cfg->n[INTEL_L3P_IS] || cfg->n[INTEL_L3P_RO] ||
640 cfg->n[INTEL_L3P_ALL];
641 const bool has_c = cfg->n[INTEL_L3P_C] || cfg->n[INTEL_L3P_RO] ||
642 cfg->n[INTEL_L3P_ALL];
643 const bool has_t = cfg->n[INTEL_L3P_T] || cfg->n[INTEL_L3P_RO] ||
644 cfg->n[INTEL_L3P_ALL];
646 assert(!cfg->n[INTEL_L3P_ALL]);
653 const bool urb_low_bw = cfg->n[INTEL_L3P_SLM] && devinfo->platform != INTEL_PLATFORM_BYT;
654 assert(!urb_low_bw || cfg->n[INTEL_L3P_URB] == cfg->n[INTEL_L3P_SLM]);
658 assert(cfg->n[INTEL_L3P_URB] >= n0_urb);
675 l3cr2.SLMEnable = cfg->n[INTEL_L3P_SLM];
677 l3cr2.URBAllocation = cfg->n[INTEL_L3P_URB] - n0_urb;
679 l3cr2.ALLAllocation = cfg->n[INTEL_L3P_ALL];
681 l3cr2.ROAllocation = cfg->n[INTEL_L3P_RO];
682 l3cr2.DCAllocation = cfg->n[INTEL_L3P_DC];
686 l3cr3.ISAllocation = cfg->n[INTEL_L3P_IS];
688 l3cr3.CAllocation = cfg->n[INTEL_L3P_C];
690 l3cr3.TAllocation = cfg->n[INTEL_L3P_T];