Lines Matching defs:batch
43 struct anv_batch *batch)
66 anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) {
71 anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) {
96 anv_batch_emit(batch, GENX(3DSTATE_SUBSLICE_HASH_TABLE), p) {
114 anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), p) {
147 anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) {
152 anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) {
163 init_common_queue_state(struct anv_queue *queue, struct anv_batch *batch)
172 genX(emit_l3_config)(batch, device, cfg);
183 anv_batch_emit(batch, GENX(STATE_BASE_ADDRESS), sba) {
236 struct anv_batch batch = {
242 anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
251 anv_batch_write_reg(&batch, GENX(CACHE_MODE_1), cm1) {
261 anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
263 anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
273 anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck);
275 genX(emit_sample_pattern)(&batch, NULL);
285 anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp);
294 anv_batch_write_reg(&batch, GENX(SAMPLER_MODE), sm) {
302 anv_batch_write_reg(&batch, GENX(HALF_SLICE_CHICKEN7), hsc7) {
307 anv_batch_write_reg(&batch, GENX(TCCNTLREG), tcc) {
314 genX(emit_slice_hashing_state)(device, &batch);
321 anv_batch_write_reg(&batch, GENX(CACHE_MODE_0), cm0) {
332 anv_batch_write_reg(&batch, GENX(CS_CHICKEN1), cc1) {
347 anv_batch_write_reg(&batch, GENX(HIZ_CHICKEN), reg) {
360 anv_batch_write_reg(&batch, GENX(COMMON_SLICE_CHICKEN1), c1) {
375 anv_batch_write_reg(&batch, AA_LINE_QUALITY_REG, c3) {
385 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
389 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
403 anv_batch_write_reg(&batch, GENX(CS_DEBUG_MODE2), csdm2) {
408 anv_batch_write_reg(&batch, GENX(INSTPM), instpm) {
415 init_common_queue_state(queue, &batch);
417 anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);
419 assert(batch.next <= batch.end);
421 return anv_queue_submit_simple_batch(queue, &batch);
427 struct anv_batch batch;
430 batch.start = batch.next = cmds;
431 batch.end = (void *) cmds + sizeof(cmds);
433 anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
444 init_common_queue_state(queue, &batch);
446 anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);
448 assert(batch.next <= batch.end);
450 return anv_queue_submit_simple_batch(queue, &batch);
591 genX(emit_l3_config)(struct anv_batch *batch,
607 anv_batch_write_reg(batch, L3_ALLOCATION_REG, l3cr) {
660 anv_batch_write_reg(batch, GENX(L3SQCREG1), l3sqc) {
674 anv_batch_write_reg(batch, GENX(L3CNTLREG2), l3cr2) {
685 anv_batch_write_reg(batch, GENX(L3CNTLREG3), l3cr3) {
699 anv_batch_write_reg(batch, GENX(SCRATCH1), s1) {
702 anv_batch_write_reg(batch, GENX(CHICKEN3), c3) {
713 genX(emit_multisample)(struct anv_batch *batch, uint32_t samples,
724 anv_batch_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
758 genX(emit_sample_pattern)(struct anv_batch *batch,
767 anv_batch_emit(batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) {
834 genX(emit_shading_rate)(struct anv_batch *batch,
842 anv_batch_emit(batch, GENX(3DSTATE_CPS), cps) {
860 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
868 anv_batch_emit(batch, GENX(3DSTATE_CPS_POINTERS), cps) {