Lines Matching defs:cmd_buffer
330 khr_perf_query_ensure_relocs(struct anv_cmd_buffer *cmd_buffer)
332 if (anv_batch_has_error(&cmd_buffer->batch))
335 if (cmd_buffer->self_mod_locations)
338 struct anv_device *device = cmd_buffer->device;
341 cmd_buffer->self_mod_locations =
342 vk_alloc(&cmd_buffer->vk.pool->alloc,
343 pdevice->n_perf_query_commands * sizeof(*cmd_buffer->self_mod_locations), 8,
346 if (!cmd_buffer->self_mod_locations) {
347 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
613 emit_ps_depth_count(struct anv_cmd_buffer *cmd_buffer,
616 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
617 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
619 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
625 if (GFX_VER == 9 && cmd_buffer->device->info.gt == 4)
639 emit_query_pc_availability(struct anv_cmd_buffer *cmd_buffer,
643 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
644 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
646 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
659 emit_zero_queries(struct anv_cmd_buffer *cmd_buffer,
676 emit_query_pc_availability(cmd_buffer,
680 emit_query_pc_availability(cmd_buffer, slot_addr, true);
730 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
736 emit_query_pc_availability(cmd_buffer,
744 emit_query_pc_availability(cmd_buffer,
753 anv_add_pending_pipe_bits(cmd_buffer, ANV_PIPE_CS_STALL_BIT,
755 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
763 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
773 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
789 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
863 emit_perf_intel_query(struct anv_cmd_buffer *cmd_buffer,
870 &cmd_buffer->device->physical->perf->query_layout;
880 anv_batch_emit(&cmd_buffer->batch, GENX(MI_REPORT_PERF_COUNT), rpc) {
923 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
928 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
932 emit_ps_depth_count(cmd_buffer, anv_address_add(query_addr, 8));
936 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
946 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
962 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
971 if (!khr_perf_query_ensure_relocs(cmd_buffer))
974 const struct anv_physical_device *pdevice = cmd_buffer->device->physical;
989 cmd_buffer->self_mod_locations[reloc_idx++] = mi_store_address(&b, reg_addr);
1000 cmd_buffer->self_mod_locations[reloc_idx++] = mi_store_address(&b, reg_addr);
1013 cmd_buffer->self_mod_locations[reloc_idx++] =
1020 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1024 cmd_buffer->perf_query_pool = pool;
1026 cmd_buffer->perf_reloc_idx = 0;
1034 dws = anv_batch_emitn(&cmd_buffer->batch,
1039 cmd_buffer->self_mod_locations[cmd_buffer->perf_reloc_idx++],
1050 anv_batch_emitn(&cmd_buffer->batch,
1056 cmd_buffer->self_mod_locations[cmd_buffer->perf_reloc_idx++],
1061 anv_batch_emitn(&cmd_buffer->batch,
1067 cmd_buffer->self_mod_locations[cmd_buffer->perf_reloc_idx++],
1083 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1087 emit_perf_intel_query(cmd_buffer, pool, &b, query_addr, false);
1110 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1115 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
1119 emit_ps_depth_count(cmd_buffer, anv_address_add(query_addr, 16));
1120 emit_query_pc_availability(cmd_buffer, query_addr, true);
1127 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1139 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1157 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1168 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1172 cmd_buffer->perf_query_pool = pool;
1174 if (!khr_perf_query_ensure_relocs(cmd_buffer))
1177 const struct anv_physical_device *pdevice = cmd_buffer->device->physical;
1186 dws = anv_batch_emitn(&cmd_buffer->batch,
1191 cmd_buffer->self_mod_locations[cmd_buffer->perf_reloc_idx++],
1202 anv_batch_emitn(&cmd_buffer->batch,
1208 cmd_buffer->self_mod_locations[cmd_buffer->perf_reloc_idx++],
1213 anv_batch_emitn(&cmd_buffer->batch,
1219 cmd_buffer->self_mod_locations[cmd_buffer->perf_reloc_idx++],
1232 anv_batch_emitn(&cmd_buffer->batch,
1237 cmd_buffer->self_mod_locations[cmd_buffer->perf_reloc_idx++],
1241 assert(cmd_buffer->perf_reloc_idx == pdevice->n_perf_query_commands);
1247 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1253 mi_imm(cmd_buffer->intel_perf_marker));
1254 emit_perf_intel_query(cmd_buffer, pool, &b, query_addr, true);
1271 if (cmd_buffer->state.gfx.view_mask) {
1273 util_bitcount(cmd_buffer->state.gfx.view_mask);
1275 emit_zero_queries(cmd_buffer, &b, pool, query + 1, num_queries - 1);
1287 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1294 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
1302 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
1303 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
1305 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1310 if (GFX_VER == 9 && cmd_buffer->device->info.gt == 4)
1313 emit_query_pc_availability(cmd_buffer, query_addr, true);
1325 if (cmd_buffer->state.gfx.view_mask) {
1327 util_bitcount(cmd_buffer->state.gfx.view_mask);
1329 emit_zero_queries(cmd_buffer, &b, pool, query + 1, num_queries - 1);
1344 gpu_write_query_result_cond(struct anv_cmd_buffer *cmd_buffer,
1355 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
1403 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1408 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
1415 if (cmd_buffer->state.pending_pipe_bits & ANV_PIPE_RENDER_TARGET_BUFFER_WRITES) {
1416 anv_add_pending_pipe_bits(cmd_buffer,
1423 (cmd_buffer->state.pending_pipe_bits & ANV_PIPE_FLUSH_BITS) ||
1437 anv_add_pending_pipe_bits(cmd_buffer,
1440 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
1456 gpu_write_query_result_cond(cmd_buffer, &b, query_addr, dest_addr,
1459 gpu_write_query_result_cond(cmd_buffer, &b, query_addr, dest_addr,
1474 if ((cmd_buffer->device->info.ver == 8 ||
1475 cmd_buffer->device->info.verx10 == 75) &&