Lines Matching refs:pipeline
91 emit_vertex_input(struct anv_graphics_pipeline *pipeline,
94 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
117 p = anv_batch_emitn(&pipeline->base.batch, num_dwords,
151 enum isl_format format = anv_get_isl_format(&pipeline->base.device->info,
185 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
186 bool per_instance = pipeline->vb[binding].instanced;
187 uint32_t divisor = pipeline->vb[binding].instance_divisor *
188 pipeline->instance_multiplier;
229 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
236 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_SGVS), sgvs) {
262 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
322 emit_urb_setup_mesh(struct anv_graphics_pipeline *pipeline,
325 const struct intel_device_info *devinfo = &pipeline->base.device->info;
328 anv_pipeline_has_stage(pipeline, MESA_SHADER_TASK) ?
329 get_task_prog_data(pipeline) : NULL;
330 const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
333 intel_get_mesh_urb_config(devinfo, pipeline->base.l3_config,
337 /* Zero out the primitive pipeline URB allocations. */
339 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_URB_VS), urb) {
344 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_URB_ALLOC_TASK), urb) {
354 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_URB_ALLOC_MESH), urb) {
367 emit_urb_setup(struct anv_graphics_pipeline *pipeline,
371 if (anv_pipeline_is_mesh(pipeline)) {
372 emit_urb_setup_mesh(pipeline, deref_block_size);
380 !anv_pipeline_has_stage(pipeline, i) ? NULL :
381 (const struct brw_vue_prog_data *) pipeline->shaders[i]->prog_data;
386 genX(emit_urb_setup)(pipeline->base.device, &pipeline->base.batch,
387 pipeline->base.l3_config,
388 pipeline->active_stages, entry_size,
393 emit_3dstate_sbe(struct anv_graphics_pipeline *pipeline)
395 const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
397 if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
398 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_SBE), sbe);
400 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_SBE_SWIZ), sbe);
403 if (anv_pipeline_is_mesh(pipeline))
404 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_SBE_MESH), sbe_mesh);
414 .AttributeSwizzleEnable = anv_pipeline_is_primitive(pipeline),
434 if (anv_pipeline_is_primitive(pipeline)) {
436 &anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map;
505 assert(anv_pipeline_is_mesh(pipeline));
507 const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
508 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_SBE_MESH), sbe_mesh) {
551 uint32_t *dw = anv_batch_emit_dwords(&pipeline->base.batch,
555 GENX(3DSTATE_SBE_pack)(&pipeline->base.batch, dw, &sbe);
558 dw = anv_batch_emit_dwords(&pipeline->base.batch, GENX(3DSTATE_SBE_SWIZ_length));
561 GENX(3DSTATE_SBE_SWIZ_pack)(&pipeline->base.batch, dw, &swiz);
571 genX(raster_polygon_mode)(struct anv_graphics_pipeline *pipeline,
574 if (anv_pipeline_is_mesh(pipeline)) {
575 switch (get_mesh_prog_data(pipeline)->primitive_type) {
581 return pipeline->polygon_mode;
585 } else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
586 switch (get_gs_prog_data(pipeline)->output_topology) {
602 return pipeline->polygon_mode;
605 } else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL)) {
606 switch (get_tes_prog_data(pipeline)->output_topology) {
615 return pipeline->polygon_mode;
634 return pipeline->polygon_mode;
643 genX(ms_rasterization_mode)(struct anv_graphics_pipeline *pipeline,
648 switch (pipeline->line_mode) {
660 return pipeline->rasterization_samples > 1 ?
740 emit_rs_state(struct anv_graphics_pipeline *pipeline,
782 if (anv_pipeline_is_primitive(pipeline)) {
784 anv_pipeline_get_last_vue_prog_data(pipeline);
787 assert(anv_pipeline_is_mesh(pipeline));
788 const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
825 raster.ViewportZFarClipTestEnable = pipeline->depth_clip_enable;
826 raster.ViewportZNearClipTestEnable = pipeline->depth_clip_enable;
828 raster.ViewportZClipTestEnable = pipeline->depth_clip_enable;
844 anv_get_isl_format(&pipeline->base.device->info,
854 GENX(3DSTATE_SF_pack)(NULL, pipeline->gfx8.sf, &sf);
855 GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gfx8.raster, &raster);
858 GENX(3DSTATE_SF_pack)(NULL, &pipeline->gfx7.sf, &sf);
863 emit_ms_state(struct anv_graphics_pipeline *pipeline,
868 genX(emit_multisample)(&pipeline->base.batch,
869 pipeline->rasterization_samples,
888 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_SAMPLE_MASK), sm) {
1000 emit_cb_state(struct anv_graphics_pipeline *pipeline,
1004 struct anv_device *device = pipeline->base.device;
1005 const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
1016 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
1017 map = &pipeline->shaders[MESA_SHADER_FRAGMENT]->bind_map;
1021 const struct intel_device_info *devinfo = &pipeline->base.device->info;
1023 pipeline->gfx8.blend_state : pipeline->gfx7.blend_state;
1151 GENX(3DSTATE_PS_BLEND_pack)(NULL, pipeline->gfx8.ps_blend, &blend);
1158 emit_3dstate_clip(struct anv_graphics_pipeline *pipeline,
1163 const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
1173 clip.APIMode = pipeline->negative_one_to_one ? APIMODE_OGL : APIMODE_D3D;
1202 if (anv_pipeline_is_primitive(pipeline)) {
1204 anv_pipeline_get_last_vue_prog_data(pipeline);
1232 } else if (anv_pipeline_is_mesh(pipeline)) {
1233 const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
1243 clip.ViewportZClipTestEnable = pipeline->depth_clip_enable;
1249 GENX(3DSTATE_CLIP_pack)(NULL, pipeline->gfx7.clip, &clip);
1252 if (anv_pipeline_is_mesh(pipeline)) {
1253 const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
1254 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_CLIP_MESH), clip_mesh) {
1264 emit_3dstate_streamout(struct anv_graphics_pipeline *pipeline,
1268 anv_pipeline_get_last_vue_prog_data(pipeline);
1272 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
1273 xfb_info = pipeline->shaders[MESA_SHADER_GEOMETRY]->xfb_info;
1274 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
1275 xfb_info = pipeline->shaders[MESA_SHADER_TESS_EVAL]->xfb_info;
1277 xfb_info = pipeline->shaders[MESA_SHADER_VERTEX]->xfb_info;
1366 if (intel_device_info_is_dg2(&pipeline->base.device->info))
1367 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_STREAMOUT), so);
1369 uint32_t *dw = anv_batch_emitn(&pipeline->base.batch, 3 + 2 * max_decls,
1392 # define streamout_state_dw pipeline->gfx7.streamout_state
1394 # define streamout_state_dw pipeline->gfx8.streamout_state
1426 pipeline->gfx7.xfb_bo_pitch[0] = xfb_info->buffers[0].stride;
1427 pipeline->gfx7.xfb_bo_pitch[1] = xfb_info->buffers[1].stride;
1428 pipeline->gfx7.xfb_bo_pitch[2] = xfb_info->buffers[2].stride;
1429 pipeline->gfx7.xfb_bo_pitch[3] = xfb_info->buffers[3].stride;
1477 get_scratch_address(struct anv_pipeline *pipeline,
1482 .bo = anv_scratch_pool_alloc(pipeline->device,
1483 &pipeline->device->scratch_pool,
1496 get_scratch_surf(struct anv_pipeline *pipeline,
1504 anv_scratch_pool_alloc(pipeline->device,
1505 &pipeline->device->scratch_pool,
1507 anv_reloc_list_add_bo(pipeline->batch.relocs,
1508 pipeline->batch.alloc, bo);
1509 return anv_scratch_pool_get_surf(pipeline->device,
1510 &pipeline->device->scratch_pool,
1515 emit_3dstate_vs(struct anv_graphics_pipeline *pipeline)
1517 const struct intel_device_info *devinfo = &pipeline->base.device->info;
1518 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
1520 pipeline->shaders[MESA_SHADER_VERTEX];
1522 assert(anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX));
1524 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VS), vs) {
1551 anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL)) {
1586 get_scratch_surf(&pipeline->base, MESA_SHADER_VERTEX, vs_bin);
1590 get_scratch_address(&pipeline->base, MESA_SHADER_VERTEX, vs_bin);
1596 emit_3dstate_hs_te_ds(struct anv_graphics_pipeline *pipeline,
1599 if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL)) {
1600 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_HS), hs);
1601 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_TE), te);
1602 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_DS), ds);
1606 const struct intel_device_info *devinfo = &pipeline->base.device->info;
1608 pipeline->shaders[MESA_SHADER_TESS_CTRL];
1610 pipeline->shaders[MESA_SHADER_TESS_EVAL];
1612 const struct brw_tcs_prog_data *tcs_prog_data = get_tcs_prog_data(pipeline);
1613 const struct brw_tes_prog_data *tes_prog_data = get_tes_prog_data(pipeline);
1615 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_HS), hs) {
1648 get_scratch_surf(&pipeline->base, MESA_SHADER_TESS_CTRL, tcs_bin);
1652 get_scratch_address(&pipeline->base, MESA_SHADER_TESS_CTRL, tcs_bin);
1668 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_TE), te) {
1700 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_DS), ds) {
1739 get_scratch_surf(&pipeline->base, MESA_SHADER_TESS_EVAL, tes_bin);
1743 get_scratch_address(&pipeline->base, MESA_SHADER_TESS_EVAL, tes_bin);
1749 emit_3dstate_gs(struct anv_graphics_pipeline *pipeline)
1751 const struct intel_device_info *devinfo = &pipeline->base.device->info;
1753 pipeline->shaders[MESA_SHADER_GEOMETRY];
1755 if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
1756 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_GS), gs);
1760 const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
1762 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_GS), gs) {
1811 get_scratch_surf(&pipeline->base, MESA_SHADER_GEOMETRY, gs_bin);
1815 get_scratch_address(&pipeline->base, MESA_SHADER_GEOMETRY, gs_bin);
1821 emit_3dstate_wm(struct anv_graphics_pipeline *pipeline,
1828 const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
1838 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
1864 pipeline->force_fragment_thread_dispatch =
1889 pipeline->force_fragment_thread_dispatch =
1908 const struct intel_device_info *devinfo = &pipeline->base.device->info;
1909 uint32_t *dws = devinfo->ver >= 8 ? pipeline->gfx8.wm : pipeline->gfx7.wm;
1914 emit_3dstate_ps(struct anv_graphics_pipeline *pipeline,
1919 &pipeline->base.device->info;
1921 pipeline->shaders[MESA_SHADER_FRAGMENT];
1923 if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
1924 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_PS), ps) {
1935 const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
1959 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_PS), ps) {
2024 get_scratch_surf(&pipeline->base, MESA_SHADER_FRAGMENT, fs_bin);
2028 get_scratch_address(&pipeline->base, MESA_SHADER_FRAGMENT, fs_bin);
2035 emit_3dstate_ps_extra(struct anv_graphics_pipeline *pipeline,
2039 const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
2041 if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
2042 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_PS_EXTRA), ps);
2046 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_PS_EXTRA), ps) {
2099 emit_3dstate_vf_statistics(struct anv_graphics_pipeline *pipeline)
2101 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_STATISTICS), vfs) {
2107 compute_kill_pixel(struct anv_graphics_pipeline *pipeline,
2111 if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
2112 pipeline->kill_pixel = false;
2116 const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
2132 pipeline->kill_pixel =
2142 emit_3dstate_primitive_replication(struct anv_graphics_pipeline *pipeline,
2145 if (!pipeline->use_primitive_replication) {
2146 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_PRIMITIVE_REPLICATION), pr);
2153 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_PRIMITIVE_REPLICATION), pr) {
2168 emit_task_state(struct anv_graphics_pipeline *pipeline)
2170 assert(anv_pipeline_is_mesh(pipeline));
2172 if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_TASK)) {
2173 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_TASK_CONTROL), zero);
2177 const struct anv_shader_bin *task_bin = pipeline->shaders[MESA_SHADER_TASK];
2179 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_TASK_CONTROL), tc) {
2182 get_scratch_surf(&pipeline->base, MESA_SHADER_TASK, task_bin);
2186 const struct intel_device_info *devinfo = &pipeline->base.device->info;
2187 const struct brw_task_prog_data *task_prog_data = get_task_prog_data(pipeline);
2191 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_TASK_SHADER), task) {
2215 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_TASK_REDISTRIB), redistrib) {
2230 emit_mesh_state(struct anv_graphics_pipeline *pipeline)
2232 assert(anv_pipeline_is_mesh(pipeline));
2234 const struct anv_shader_bin *mesh_bin = pipeline->shaders[MESA_SHADER_MESH];
2236 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_MESH_CONTROL), mc) {
2239 get_scratch_surf(&pipeline->base, MESA_SHADER_MESH, mesh_bin);
2243 const struct intel_device_info *devinfo = &pipeline->base.device->info;
2244 const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
2262 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_MESH_SHADER), mesh) {
2293 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_MESH_DISTRIB), distrib) {
2302 genX(graphics_pipeline_emit)(struct anv_graphics_pipeline *pipeline,
2306 emit_urb_setup(pipeline, &urb_deref_block_size);
2309 emit_rs_state(pipeline, state->ia, state->rs, state->ms, state->rp,
2311 emit_ms_state(pipeline, state->ms);
2312 emit_cb_state(pipeline, state->cb, state->ms);
2313 compute_kill_pixel(pipeline, state->ms, state->rp);
2315 emit_3dstate_clip(pipeline, state->ia, state->vp, state->rs);
2318 emit_3dstate_primitive_replication(pipeline, state->rp);
2329 * whole fixed function pipeline when the GS enable changes value in
2333 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2340 if (anv_pipeline_is_primitive(pipeline)) {
2341 emit_vertex_input(pipeline, state->vi);
2343 emit_3dstate_vs(pipeline);
2344 emit_3dstate_hs_te_ds(pipeline, state->ts);
2345 emit_3dstate_gs(pipeline);
2347 emit_3dstate_vf_statistics(pipeline);
2349 emit_3dstate_streamout(pipeline, state->rs);
2352 const struct anv_device *device = pipeline->base.device;
2355 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_MESH_CONTROL), zero);
2356 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_TASK_CONTROL), zero);
2360 assert(anv_pipeline_is_mesh(pipeline));
2365 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_STREAMOUT), so) {}
2368 emit_task_state(pipeline);
2369 emit_mesh_state(pipeline);
2373 emit_3dstate_sbe(pipeline);
2374 emit_3dstate_wm(pipeline, state->ia, state->rs,
2376 emit_3dstate_ps(pipeline, state->ms, state->cb);
2378 emit_3dstate_ps_extra(pipeline, state->rs, state->rp);
2385 genX(compute_pipeline_emit)(struct anv_compute_pipeline *pipeline)
2387 struct anv_device *device = pipeline->base.device;
2388 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
2389 anv_pipeline_setup_l3_config(&pipeline->base, cs_prog_data->base.total_shared > 0);
2391 const UNUSED struct anv_shader_bin *cs_bin = pipeline->cs;
2394 anv_batch_emit(&pipeline->base.batch, GENX(CFE_STATE), cfe) {
2398 get_scratch_surf(&pipeline->base, MESA_SHADER_COMPUTE, cs_bin);
2405 genX(compute_pipeline_emit)(struct anv_compute_pipeline *pipeline)
2407 struct anv_device *device = pipeline->base.device;
2409 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
2411 anv_pipeline_setup_l3_config(&pipeline->base, cs_prog_data->base.total_shared > 0);
2419 const struct anv_shader_bin *cs_bin = pipeline->cs;
2421 anv_batch_emit(&pipeline->base.batch, GENX(MEDIA_VFE_STATE), vfe) {
2460 get_scratch_address(&pipeline->base, MESA_SHADER_COMPUTE, cs_bin);
2503 pipeline->interface_descriptor_data,
2512 genX(ray_tracing_pipeline_emit)(struct anv_ray_tracing_pipeline *pipeline)
2514 for (uint32_t i = 0; i < pipeline->group_count; i++) {
2515 struct anv_rt_shader_group *group = &pipeline->groups[i];
2553 genX(ray_tracing_pipeline_emit)(struct anv_ray_tracing_pipeline *pipeline)