Lines Matching refs:set
178 * just set them all to the maximum.
201 * To avoid this and other potential problems, we may as well set it
294 * always set for GPGPU workloads when “Texture Cache Invalidation
295 * Enable” bit is set".
650 /* If will_full_fast_clear is set, the caller promises to fast-clear the
721 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
757 /* If will_full_fast_clear is set, the caller promises to fast-clear the
1140 * command streamer stall bit set.
1393 /* If will_full_fast_clear is set, the caller promises to
1423 /* If will_full_fast_clear is set, the caller promises to fast-clear
1525 /* If will_full_fast_clear is set, the caller promises to fast-clear
1632 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1635 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1995 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
2084 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
2110 * be set with any PIPE_CONTROL with Depth Flush Enable bit set.
2128 * "This bit must be always set when PIPE_CONTROL command is
2130 * when only Read Only Cache Invalidation bits are set (State
2165 * Immediate Data, Required Write Cache Flush bits set)
2177 * "Command Streamer Stall" bit set must also have another bit set,
2221 * Immediate Data, Required Write Cache Flush bits set)
2254 * "If the VF Cache Invalidation Enable is set to a 1 in a
2256 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
2257 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
2272 * when VERTEX_BUFFER_STATE::L3BypassDisable is set.
2288 * always set for GPGPU workloads when “Texture Cache
2289 * Invalidation Enable” bit is set".
2299 * "When VF Cache Invalidate is set “Post Sync Operation” must be
2598 switch (binding->set) {
2668 /* This is a descriptor set buffer so the set index is actually
2671 struct anv_descriptor_set *set =
2673 assert(set->desc_mem.alloc_size);
2674 assert(set->desc_surface_state.alloc_size);
2675 bt_map[s] = set->desc_surface_state.offset + state_offset;
2676 add_surface_reloc(cmd_buffer, set->desc_surface_state,
2677 anv_descriptor_set_address(set));
2682 assert(binding->set < MAX_SETS);
2683 const struct anv_descriptor_set *set =
2684 pipe_state->descriptors[binding->set];
2685 if (binding->index >= set->descriptor_count) {
2691 * descriptor set must not be used."
2698 assert(binding->index < set->layout->descriptor_count);
2701 const struct anv_descriptor *desc = &set->descriptors[binding->index];
2738 "set and the image does not have a "
2746 "set and the image does not have a "
2875 &pipe_state->descriptors[binding->set]->descriptors[binding->index];
3018 switch (range->set) {
3020 /* This is a descriptor set buffer so the set index is
3024 struct anv_descriptor_set *set =
3026 return anv_descriptor_set_address(set);
3048 assert(range->set < MAX_SETS);
3049 struct anv_descriptor_set *set =
3050 gfx_state->base.descriptors[range->set];
3052 &set->descriptors[range->index];
3097 switch (range->set) {
3099 struct anv_descriptor_set *set =
3101 assert(range->start * 32 < set->desc_mem.alloc_size);
3102 assert((range->start + range->length) * 32 <= set->desc_mem.alloc_size);
3103 return set->desc_mem.alloc_size;
3113 assert(range->set < MAX_SETS);
3114 struct anv_descriptor_set *set =
3115 gfx_state->base.descriptors[range->set];
3117 &set->descriptors[range->index];
3121 * We use the descriptor set's internally allocated surface state to fill the binding table entry.
3224 /* For Ivy Bridge, make sure we only set the first range (actual
3239 assert(bind_map->push_ranges[0].set ==
3600 * set from a previous command. Also, from the Vulkan 1.3.207:
3605 * If the client doesn't set a scissor, that basically means it
3979 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
4757 * so we emit MI_PREDICATE to set it.
5710 /* Allocate and set up our RT_DISPATCH_GLOBALS */
5917 * with Pipeline Select set to GPGPU.
5989 * workaround the issue, this mode bit should be set after a pipeline
6027 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
6028 * Depth Flush Bit set, followed by another pipelined depth stall
6029 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
6904 /* Finally, now that we know the right size, set up the null surface */
6950 * is set due to new association of BTI, PS Scoreboard Stall bit must
6951 * be set in this packet."
7181 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and