Lines Matching refs:depth
126 * clear depth, reset state base address, and then go render stuff.
476 /* We don't do any HiZ or depth fast-clears on gfx7 yet */
484 /* We must have depth in order to have HiZ */
567 assert(layer < image->vk.extent.depth);
568 if (layer >= anv_minify(image->vk.extent.depth, level))
623 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
624 * the initial layout is undefined, the HiZ buffer and depth buffer will
651 * largest portion of the specified range as it can. For depth images,
703 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
704 * the initial layout is undefined, the HiZ buffer and depth buffer will
1206 const uint32_t max_depth = anv_minify(image->vk.extent.depth, base_level);
2034 * synchronization that requires that the render cache and/or depth
2039 * surface) a previous render target and/or depth/stencil buffer
2427 layer_count = anv_minify(image->vk.extent.depth, range->baseMipLevel);
3979 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
5867 uint32_t depth)
5877 width, height, depth,
5898 0, 0, 0, /* width, height, depth, */
6026 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
6027 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
6028 * Depth Flush Bit set, followed by another pipelined depth stall
6071 /* We'll change some CHICKEN registers depending on the depth surface
6072 * format. Do a depth flush and stall so the pipeline is not using these
6729 depth_clear_value = d_att->clearValue.depthStencil.depth;
7122 * result of writes to the MSAA depth attachments show up in the sampler
7146 * depth attachment first to get rid of any HiZ that we may not be