Lines Matching defs:state
103 /* If we are emitting a new state base address we probably need to re-emit
106 cmd_buffer->state.descriptors_dirty |= ~0;
124 * necessary prior to changing the surface state base address. Without
126 * clear depth, reset state base address, and then go render stuff.
142 * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
145 uint32_t gfx12_wa_pipeline = cmd_buffer->state.current_pipeline;
240 /* After re-setting the surface state base address, we have to do some
245 * Coherency with system memory in the state cache, like the texture
254 * Surface_State_Base_Addr are altered, the L1 state cache must be
255 * invalidated to ensure the new surface or sampler state is fetched
263 * This bit controls the invalidation of the L1 and L2 state caches
266 * Unfortunately, experimentation seems to indicate that state cache
268 * regards to surface state and binding tables. In stead, it seems that
300 cmd_buffer->state.current_pipeline == GPGPU;
308 struct anv_state state, struct anv_address addr)
316 state.offset + isl_dev->ss.addr_offset,
330 struct anv_surface_state state)
334 assert(!anv_address_is_null(state.address));
335 add_surface_reloc(cmd_buffer, state.state, state.address);
337 if (!anv_address_is_null(state.aux_address)) {
341 state.state.offset + isl_dev->ss.aux_addr_offset,
342 state.aux_address.bo,
343 state.aux_address.offset,
349 if (!anv_address_is_null(state.clear_address)) {
353 state.state.offset +
355 state.clear_address.bo,
356 state.clear_address.offset,
676 /* Getting into the pass-through state for Depth is tricky and involves
677 * both a resolve and an ambiguate. We don't handle that state right now
887 * colors. We don't care about the compression state but we do care
954 * state into the predicate register.
1040 * track the current fast-clear and compression state. This leaves us
1102 /* Copy the fast-clear value dword(s) between a surface state object and an
1103 * image's fast clear state buffer.
1136 * fact that we're using a GPU state register as our temporary and that
1156 /* Updating a surface state object may require that the state cache be
1162 * modified [...], the L1 state cache must be invalidated to ensure
1163 * the new surface or sampler state is fetched from system memory.
1169 "after copy_fast_clear_dwords surface state update");
1292 /* The fast clear state lives in a driver-private bo, and therefore the
1296 * clear state is uninitialized.
1299 * clear state may still be valid and correct due to the resolve during
1301 * state with MI stores, and therefore must assume the worst-case: that
1312 /* The aux surface, like the fast clear state, lives in
1314 * same reasons we must initialize the fast clear state.
1320 /* The aux surface, unlike the fast clear state, lives in
1324 * the aux state required by the modifier.
1364 * pass-through state so that, if we then go to texture from the
1370 * transition the aux surface into the pass-through state.
1464 * image. Doing so in a performant way requires more detailed aux state
1566 struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
1568 /* Reserve one for the NULL state. */
1590 .surface_state.state = next_state,
1604 struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
1625 * command buffer's state. Otherwise, we must *reset* its state. In both
1630 * If a command buffer is in the executable state and the command buffer
1636 * the command buffer in the recording state.
1659 /* We sometimes store vertex data in the dynamic state buffer for blorp
1660 * operations and our dynamic state stream may re-use data from previous
1692 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_ALL_GRAPHICS;
1696 struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
1731 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
1755 cmd_buffer->state.conditional_render_enabled =
1768 * control packet, the indirect state pointers in the hardware are
1770 * If any new indirect state commands are executed in the command stream
1771 * while the pipe control is pending, the new indirect state commands are
1825 /* We want every command buffer to start with the PMA fix in a known state,
1871 if (secondary->state.conditional_render_enabled) {
1872 if (!primary->state.conditional_render_enabled) {
1893 struct anv_state src_state = primary->state.gfx.att_states;
1894 struct anv_state dst_state = secondary->state.gfx.att_states;
1917 if (secondary->state.depth_reg_mode != ANV_DEPTH_REG_MODE_UNKNOWN)
1918 primary->state.depth_reg_mode = secondary->state.depth_reg_mode;
1937 primary->state.current_pipeline = UINT32_MAX;
1938 primary->state.current_l3_config = NULL;
1939 primary->state.current_hash_scale = 0;
1940 primary->state.gfx.push_constant_stages = 0;
1943 /* Each of the secondary command buffers will use its own state base
1944 * address. We need to re-emit state base address for the primary after
1947 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1961 if (cfg == cmd_buffer->state.current_l3_config)
2021 cmd_buffer->state.current_l3_config = cfg;
2329 /* If we're changing the state of the RHWO optimization, we need to have
2333 cmd_buffer->state.rhwo_optimization_enabled !=
2334 cmd_buffer->state.pending_rhwo_optimization_enabled;
2343 enum anv_pipe_bits bits = cmd_buffer->state.pending_pipe_bits;
2361 memset(cmd_buffer->state.gfx.vb_dirty_ranges, 0,
2362 sizeof(cmd_buffer->state.gfx.vb_dirty_ranges));
2363 memset(&cmd_buffer->state.gfx.ib_dirty_range, 0,
2364 sizeof(cmd_buffer->state.gfx.ib_dirty_range));
2367 cmd_buffer->state.pending_pipe_bits =
2370 cmd_buffer->state.current_pipeline,
2378 !cmd_buffer->state.pending_rhwo_optimization_enabled;
2381 cmd_buffer->state.rhwo_optimization_enabled =
2382 cmd_buffer->state.pending_rhwo_optimization_enabled;
2488 cmd_buffer->state.gfx.pipeline->active_stages;
2496 if (anv_pipeline_is_primitive(cmd_buffer->state.gfx.pipeline))
2499 if (stages == cmd_buffer->state.gfx.push_constant_stages)
2550 cmd_buffer->state.gfx.push_constant_stages = stages;
2561 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_ALL_GRAPHICS;
2606 if (binding->index < cmd_buffer->state.gfx.color_att_count) {
2608 &cmd_buffer->state.gfx.color_att[binding->index];
2609 surface_state = att->surface_state.state;
2611 surface_state = cmd_buffer->state.gfx.null_surface_state;
2655 cmd_buffer->state.compute.num_workgroups,
2662 cmd_buffer->state.compute.num_workgroups);
2717 surface_state = sstate.state;
2733 surface_state = sstate.state;
2858 struct anv_state *state)
2862 *state = (struct anv_state) { 0, };
2867 *state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, 32);
2869 if (state->map == NULL)
2889 memcpy(state->map + (s * 16),
2890 sampler->state[binding->plane], sizeof(sampler->state[0]));
2915 assert(stage < ARRAY_SIZE(cmd_buffer->state.samplers));
2917 &cmd_buffer->state.samplers[stage]);
2921 assert(stage < ARRAY_SIZE(cmd_buffer->state.binding_tables));
2923 &cmd_buffer->state.binding_tables[stage]);
2937 /* Re-emit state base addresses so we get the new surface state base
2952 &cmd_buffer->state.samplers[stage]);
2958 &cmd_buffer->state.binding_tables[stage]);
2994 if (cmd_buffer->state.samplers[s].alloc_size > 0) {
2998 ssp.PointertoVSSamplerState = cmd_buffer->state.samplers[s].offset;
3007 btp.PointertoVSBindingTable = cmd_buffer->state.binding_tables[s].offset;
3017 struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
3096 const struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
3121 * We use the descriptor set's internally allocated surface state to fill the binding table entry.
3161 const struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
3234 /* For Ivy Bridge, push constants are relative to dynamic state
3270 const struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
3315 struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
3353 cmd_buffer->state.push_constants_dirty |=
3361 /* Resets the push constant state so that we allocate a new one if
3426 cmd_buffer->state.push_constants_dirty &= ~flushed;
3434 struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
3454 cmd_buffer->state.gfx.base.push_constants.client_data,
3477 cmd_buffer->state.gfx.base.push_constants.client_data,
3483 cmd_buffer->state.push_constants_dirty &= ~dirty_stages;
3493 if (!(cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) &&
3506 genX(raster_polygon_mode)(cmd_buffer->state.gfx.pipeline,
3521 struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
3545 struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
3554 cmd_buffer->state.gfx.pipeline->negative_one_to_one;
3561 /* The gfx7 state struct has just the matrix and guardband fields, the
3695 struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
3703 * "The viewport-specific state used by the SF unit (SCISSOR_RECT) is
3775 struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
3796 struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
3811 * the GPU will read the state at weird times.
3815 uint32_t vb_emit = cmd_buffer->state.gfx.vb_dirty & pipeline->vb_used;
3816 if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE)
3827 struct anv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
3828 uint32_t offset = cmd_buffer->state.vertex_bindings[vb].offset;
3830 struct GENX(VERTEX_BUFFER_STATE) state;
3833 UNUSED uint32_t size = cmd_buffer->state.vertex_bindings[vb].size;
3841 state = (struct GENX(VERTEX_BUFFER_STATE)) {
3870 state = (struct GENX(VERTEX_BUFFER_STATE)) {
3880 state.BufferStartingAddress,
3881 state.BufferSize);
3884 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, &p[1 + i * 4], &state);
3889 cmd_buffer->state.gfx.vb_dirty &= ~vb_emit;
3891 uint32_t descriptors_dirty = cmd_buffer->state.descriptors_dirty &
3893 if (!cmd_buffer->state.gfx.dirty && !descriptors_dirty &&
3895 !cmd_buffer->state.push_constants_dirty)
3898 if ((cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_XFB_ENABLE) ||
3899 (GFX_VER == 7 && (cmd_buffer->state.gfx.dirty &
3905 * state is not combined with other state changes.
3918 struct anv_xfb_binding *xfb = &cmd_buffer->state.xfb_bindings[idx];
3927 if (cmd_buffer->state.xfb_enabled && xfb->buffer && xfb->size != 0) {
3965 if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) {
3975 if (cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_VERTEX_BIT ||
3976 cmd_buffer->state.push_constants_dirty & VK_SHADER_STAGE_VERTEX_BIT) {
3997 if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_RENDER_TARGETS)
4010 &cmd_buffer->state.gfx.base,
4014 cmd_buffer->state.descriptors_dirty &= ~dirty;
4017 if (dirty || cmd_buffer->state.push_constants_dirty) {
4021 dirty |= cmd_buffer->state.push_constants_dirty;
4038 if ((cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
4043 if ((cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
4053 if ((cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) ||
4061 cmd_buffer->state.gfx.primitive_topology = topology;
4137 struct anv_state state =
4140 ((uint32_t *)state.map)[0] = draw_index;
4144 .offset = state.offset,
4154 struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
4202 struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
4217 if (cmd_buffer->state.conditional_render_enabled)
4225 prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
4227 prim.PrimitiveTopologyType = cmd_buffer->state.gfx.primitive_topology;
4250 struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
4265 if (cmd_buffer->state.conditional_render_enabled)
4275 prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
4277 prim.PrimitiveTopologyType = cmd_buffer->state.gfx.primitive_topology;
4301 struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
4317 if (cmd_buffer->state.conditional_render_enabled)
4323 prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
4325 prim.PrimitiveTopologyType = cmd_buffer->state.gfx.primitive_topology;
4349 struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
4365 if (cmd_buffer->state.conditional_render_enabled)
4389 prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
4391 prim.PrimitiveTopologyType = cmd_buffer->state.gfx.primitive_topology;
4412 prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
4414 prim.PrimitiveTopologyType = cmd_buffer->state.gfx.primitive_topology;
4431 prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
4433 prim.PrimitiveTopologyType = cmd_buffer->state.gfx.primitive_topology;
4469 struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
4486 if (cmd_buffer->state.conditional_render_enabled)
4518 prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
4520 prim.PrimitiveTopologyType = cmd_buffer->state.gfx.primitive_topology;
4535 struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
4579 struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
4593 if (cmd_buffer->state.conditional_render_enabled)
4614 prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
4616 prim.PrimitiveTopologyType = cmd_buffer->state.gfx.primitive_topology;
4636 struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
4650 if (cmd_buffer->state.conditional_render_enabled)
4672 prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
4674 prim.PrimitiveTopologyType = cmd_buffer->state.gfx.primitive_topology;
4696 if (cmd_buffer->state.conditional_render_enabled) {
4779 if (cmd_buffer->state.conditional_render_enabled) {
4802 struct anv_cmd_state *cmd_state = &cmd_buffer->state;
4845 prim.PrimitiveTopologyType = cmd_buffer->state.gfx.primitive_topology;
4870 struct anv_cmd_state *cmd_state = &cmd_buffer->state;
4914 prim.PrimitiveTopologyType = cmd_buffer->state.gfx.primitive_topology;
4979 cmd_buffer->state.xfb_enabled = true;
4980 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_XFB_ENABLE;
5029 cmd_buffer->state.xfb_enabled = false;
5030 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_XFB_ENABLE;
5048 if (cmd_buffer->state.conditional_render_enabled)
5057 m.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
5111 struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
5114 struct anv_cmd_state *cmd_state = &cmd_buffer->state;
5154 struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
5190 struct anv_cmd_compute_state *comp_state = &cmd_buffer->state.compute;
5201 * the GPU will read the state at weird times.
5205 if (cmd_buffer->state.compute.pipeline_dirty) {
5216 "flush compute state");
5224 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
5227 if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
5228 cmd_buffer->state.compute.pipeline_dirty) {
5230 &cmd_buffer->state.compute.base,
5233 cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
5239 cmd_buffer->state.binding_tables[MESA_SHADER_COMPUTE].offset,
5241 cmd_buffer->state.samplers[MESA_SHADER_COMPUTE].offset,
5245 struct anv_state state =
5255 mid.InterfaceDescriptorDataStartAddress = state.offset;
5260 if (cmd_buffer->state.push_constants_dirty & VK_SHADER_STAGE_COMPUTE_BIT) {
5273 cmd_buffer->state.push_constants_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
5276 cmd_buffer->state.compute.pipeline_dirty = false;
5309 &cmd_buffer->state.compute.base.push_constants;
5317 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
5339 struct anv_cmd_compute_state *comp_state = &cmd_buffer->state.compute;
5341 bool predicate = cmd_buffer->state.conditional_render_enabled;
5365 cmd_buffer->state.samplers[MESA_SHADER_COMPUTE].offset,
5367 cmd_buffer->state.binding_tables[MESA_SHADER_COMPUTE].offset,
5388 cmd_buffer->state.conditional_render_enabled;
5439 struct anv_compute_pipeline *pipeline = cmd_buffer->state.compute.pipeline;
5458 struct anv_state state =
5460 uint32_t *sizes = state.map;
5464 cmd_buffer->state.compute.num_workgroups = (struct anv_address) {
5466 .offset = state.offset,
5470 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
5475 if (cmd_buffer->state.conditional_render_enabled)
5496 struct anv_compute_pipeline *pipeline = cmd_buffer->state.compute.pipeline;
5519 cmd_buffer->state.compute.num_workgroups = addr;
5522 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
5572 if (cmd_buffer->state.conditional_render_enabled) {
5585 if (cmd_buffer->state.conditional_render_enabled)
5600 struct anv_state state =
5624 .bo = cmd_buffer->state.ray_query_shadow_bo,
5627 GFX_RT_DISPATCH_GLOBALS_pack(NULL, state.map, &rtdg);
5629 return state;
5683 struct anv_cmd_ray_tracing_state *rt = &cmd_buffer->state.rt;
5697 cmd_buffer->state.rt.pipeline_dirty = false;
5741 &cmd_buffer->state.rt.base.push_constants,
5831 struct anv_state *surfaces = &cmd_buffer->state.binding_tables[s];
5832 struct anv_state *samplers = &cmd_buffer->state.samplers[s];
5909 if (cmd_buffer->state.current_pipeline == pipeline)
5946 cmd_buffer->state.compute.pipeline_dirty = true;
6000 cmd_buffer->state.current_pipeline = pipeline;
6023 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
6058 switch (cmd_buffer->state.depth_reg_mode) {
6092 cmd_buffer->state.depth_reg_mode =
6137 bound = &cmd_buffer->state.gfx.ib_bound_range;
6138 dirty = &cmd_buffer->state.gfx.ib_dirty_range;
6141 assert(vb_index < ARRAY_SIZE(cmd_buffer->state.gfx.vb_bound_ranges));
6142 assert(vb_index < ARRAY_SIZE(cmd_buffer->state.gfx.vb_dirty_ranges));
6143 bound = &cmd_buffer->state.gfx.vb_bound_ranges[vb_index];
6144 dirty = &cmd_buffer->state.gfx.vb_dirty_ranges[vb_index];
6168 struct anv_vb_cache_range *bound = &cmd_buffer->state.gfx.ib_bound_range;
6169 struct anv_vb_cache_range *dirty = &cmd_buffer->state.gfx.ib_dirty_range;
6181 assert(i < ARRAY_SIZE(cmd_buffer->state.gfx.vb_bound_ranges));
6182 assert(i < ARRAY_SIZE(cmd_buffer->state.gfx.vb_dirty_ranges));
6185 bound = &cmd_buffer->state.gfx.vb_bound_ranges[i];
6186 dirty = &cmd_buffer->state.gfx.vb_dirty_ranges[i];
6266 if (cmd_buffer->state.current_hash_scale != scale &&
6281 cmd_buffer->state.current_hash_scale = scale;
6290 struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
6391 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
6398 * have an additional pipe control after the stencil state whenever
6399 * the surface state bits of this state is changing).
6408 cmd_buffer->state.hiz_enabled = isl_aux_usage_has_hiz(info.hiz_usage);
6463 struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
6681 gfx->color_att[i].surface_state.state,
6915 gfx->color_att[i].surface_state.state.map,
6969 struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
7016 struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
7075 struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
7250 struct anv_cmd_state *cmd_state = &cmd_buffer->state;
7290 struct anv_cmd_state *cmd_state = &cmd_buffer->state;
7322 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
7335 event->state.offset
7350 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
7363 event->state.offset
7388 event->state.offset
7436 cmd_buffer->state.gfx.restart_index = restart_index_for_type(indexType);
7437 cmd_buffer->state.gfx.index_buffer = buffer;
7438 cmd_buffer->state.gfx.index_type = vk_to_intel_index_type(indexType);
7439 cmd_buffer->state.gfx.index_offset = offset;
7441 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;