Lines Matching defs:image
391 anv_image_aux_layers(iview->image, VK_IMAGE_ASPECT_COLOR_BIT,
400 anv_layout_to_fast_clear_type(&device->info, iview->image,
435 &iview->image->planes[0].primary_surface.isl,
443 /* We only allow fast clears to the first slice of an image (level 0,
445 * any given time, there is only one clear color on any given image at
452 anv_perf_warn(VK_LOG_OBJS(&iview->image->vk.base),
460 anv_perf_warn(VK_LOG_OBJS(&iview->image->vk.base),
485 if (!(iview->image->vk.aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
489 anv_layout_to_aux_usage(&device->info, iview->image,
494 &iview->image->planes[0].primary_surface.isl,
513 if (GFX_VER == 8 && anv_can_sample_with_hiz(&device->info, iview->image))
525 const struct anv_image *image,
530 const uint32_t plane = anv_image_aspect_to_plane(image, aspect);
532 const struct anv_surface *surface = &image->planes[plane].primary_surface;
534 anv_address_physical(anv_image_address(image, &surface->memory_range));
536 const struct isl_surf *isl_surf = &image->planes[plane].primary_surface.isl;
560 if (image->vk.image_type == VK_IMAGE_TYPE_3D) {
567 assert(layer < image->vk.extent.depth);
568 if (layer >= anv_minify(image->vk.extent.depth, level))
572 assert(layer < image->vk.array_layers);
610 if (isl_aux_usage_has_ccs(image->planes[plane].aux_usage))
629 const struct anv_image *image,
636 anv_image_aspect_to_plane(image, VK_IMAGE_ASPECT_DEPTH_BIT);
637 if (image->planes[depth_plane].aux_usage == ISL_AUX_USAGE_NONE)
645 anv_image_init_aux_tt(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
652 * that means the entire image because we don't support multi-LOD HiZ.
654 assert(image->planes[0].primary_surface.isl.levels == 1);
659 anv_layout_to_aux_state(&cmd_buffer->device->info, image,
663 anv_layout_to_aux_state(&cmd_buffer->device->info, image,
684 anv_image_hiz_op(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
688 anv_image_hiz_op(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
709 const struct anv_image *image,
718 anv_image_aspect_to_plane(image, VK_IMAGE_ASPECT_STENCIL_BIT);
736 if (anv_surface_is_valid(&image->planes[plane].shadow_surface) &&
739 anv_image_copy_to_shadow(cmd_buffer, image,
746 anv_image_aspect_to_plane(image, VK_IMAGE_ASPECT_STENCIL_BIT);
747 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE)
754 anv_image_init_aux_tt(cmd_buffer, image, VK_IMAGE_ASPECT_STENCIL_BIT,
768 .extent.width = anv_minify(image->vk.extent.width, level),
769 .extent.height = anv_minify(image->vk.extent.height, level),
773 anv_image_aux_layers(image, VK_IMAGE_ASPECT_STENCIL_BIT, level);
783 anv_image_hiz_clear(cmd_buffer, image, VK_IMAGE_ASPECT_STENCIL_BIT,
797 const struct anv_image *image,
803 const uint32_t plane = anv_image_aspect_to_plane(image, aspect);
806 if (image->planes[plane].aux_usage != ISL_AUX_USAGE_CCS_E)
813 image, aspect,
822 const struct anv_image *image,
828 image, aspect);
836 set_image_compressed_bit(cmd_buffer, image, aspect, 0, 0, 1, true);
845 const struct anv_image *image,
856 image, aspect));
869 image, aspect,
893 /* We need to compute (fast_clear_supported < image->fast_clear) */
928 const struct anv_image *image,
939 image, aspect));
970 const struct anv_image *image,
978 const uint32_t plane = anv_image_aspect_to_plane(image, aspect);
981 anv_cmd_compute_resolve_predicate(cmd_buffer, image,
985 anv_cmd_simple_resolve_predicate(cmd_buffer, image,
994 image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_D)
997 anv_image_ccs_op(cmd_buffer, image, format, swizzle, aspect,
1003 const struct anv_image *image,
1015 anv_cmd_compute_resolve_predicate(cmd_buffer, image,
1019 anv_image_mcs_op(cmd_buffer, image, format, swizzle, aspect,
1028 const struct anv_image *image,
1035 /* The aspect must be exactly one of the image aspects. */
1036 assert(util_bitcount(aspect) == 1 && (aspect & image->vk.aspects));
1047 set_image_compressed_bit(cmd_buffer, image, aspect,
1053 const struct anv_image *image,
1056 assert(cmd_buffer && image);
1057 assert(image->vk.aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
1059 set_image_fast_clear_state(cmd_buffer, image, aspect,
1066 anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect);
1103 * image's fast clear state buffer.
1108 const struct anv_image *image,
1112 assert(cmd_buffer && image);
1113 assert(image->vk.aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
1121 anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect);
1186 const struct anv_image *image,
1200 assert(image && image->vk.aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
1206 const uint32_t max_depth = anv_minify(image->vk.extent.depth, base_level);
1207 UNUSED const uint32_t image_layers = MAX2(image->vk.array_layers, max_depth);
1209 assert(last_level_num <= image->vk.mip_levels);
1217 image->vk.tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT
1218 ? isl_drm_modifier_get_info(image->vk.drm_format_mod)
1233 * image has a DRM format modifier because we store image data in
1238 anv_image_is_externally_shared(image) &&
1239 anv_image_has_private_binding(image);
1243 anv_image_is_externally_shared(image) &&
1244 anv_image_has_private_binding(image);
1252 const uint32_t plane = anv_image_aspect_to_plane(image, aspect);
1254 if (anv_surface_is_valid(&image->planes[plane].shadow_surface) &&
1256 /* This surface is a linear compressed image with a tiled shadow surface
1260 assert(image->vk.tiling != VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT);
1261 assert(image->vk.aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1262 assert(image->planes[plane].primary_surface.isl.tiling == ISL_TILING_LINEAR);
1263 assert(image->planes[plane].shadow_surface.isl.tiling != ISL_TILING_LINEAR);
1264 assert(isl_format_is_compressed(image->planes[plane].primary_surface.isl.format));
1266 anv_image_copy_to_shadow(cmd_buffer, image,
1272 if (base_layer >= anv_image_aux_layers(image, aspect, base_level))
1275 assert(image->planes[plane].primary_surface.isl.tiling != ISL_TILING_LINEAR);
1295 * If this is the first time we are accessing the image, then the fast
1298 * If this is NOT the first time we are accessing the image, then the fast
1302 * this is the first time we are accessing the image.
1304 assert(image->planes[plane].fast_clear_memory_range.binding ==
1308 if (image->planes[plane].aux_surface.memory_range.binding ==
1323 * image with a defined VkImageLayout, the aux surface is valid and has
1333 anv_image_init_aux_tt(cmd_buffer, image, aspect,
1344 init_fast_clear_color(cmd_buffer, image, aspect);
1363 * image as a storage image, then we must have the aux buffer in the
1365 * image, we get the results of our storage image writes and not the
1381 * and texture (no image load store).
1383 if (image->vk.samples == 1) {
1387 uint32_t aux_layers = anv_image_aux_layers(image, aspect, level);
1404 anv_image_ccs_op(cmd_buffer, image,
1405 image->planes[plane].primary_surface.isl.format,
1410 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E) {
1411 set_image_compressed_bit(cmd_buffer, image, aspect,
1417 if (image->vk.samples == 4 || image->vk.samples == 16) {
1418 anv_perf_warn(VK_LOG_OBJS(&image->vk.base),
1430 anv_image_mcs_op(cmd_buffer, image,
1431 image->planes[plane].primary_surface.isl.format,
1440 anv_layout_to_aux_usage(devinfo, image, aspect, 0, initial_layout);
1442 anv_layout_to_aux_usage(devinfo, image, aspect, 0, final_layout);
1444 anv_layout_to_fast_clear_type(devinfo, image, aspect, initial_layout);
1446 anv_layout_to_fast_clear_type(devinfo, image, aspect, final_layout);
1464 * image. Doing so in a performant way requires more detailed aux state
1516 uint32_t aux_layers = anv_image_aux_layers(image, aspect, level);
1532 if (image->vk.samples == 1) {
1533 anv_cmd_predicated_ccs_resolve(cmd_buffer, image,
1534 image->planes[plane].primary_surface.isl.format,
1547 anv_cmd_predicated_mcs_resolve(cmd_buffer, image,
1548 image->planes[plane].primary_surface.isl.format,
2421 ANV_FROM_HANDLE(anv_image, image, img_barrier->image);
2425 if (image->vk.image_type == VK_IMAGE_TYPE_3D) {
2427 layer_count = anv_minify(image->vk.extent.depth, range->baseMipLevel);
2430 layer_count = vk_image_subresource_layer_count(&image->vk, range);
2433 vk_image_subresource_level_count(&image->vk, range);
2436 transition_depth_buffer(cmd_buffer, image,
2444 transition_stencil_buffer(cmd_buffer, image,
2454 vk_image_expand_aspect_mask(&image->vk, range->aspectMask);
2455 anv_foreach_image_aspect_bit(aspect_bit, image, color_aspects) {
2456 transition_color_buffer(cmd_buffer, image, 1UL << aspect_bit,
2736 mesa_loge("Bound a image to a descriptor where the "
2738 "set and the image does not have a "
2744 "Bound a image to a descriptor where the "
2746 "set and the image does not have a "
6325 const struct anv_image *image = iview->image;
6328 anv_image_aspect_to_plane(image, VK_IMAGE_ASPECT_DEPTH_BIT);
6330 &image->planes[depth_plane].primary_surface;
6332 anv_image_address(image, &depth_surface->memory_range);
6348 &image->planes[depth_plane].aux_surface;
6350 anv_image_address(image, &hiz_surface->memory_range);
6365 const struct anv_image *image = iview->image;
6368 anv_image_aspect_to_plane(image, VK_IMAGE_ASPECT_STENCIL_BIT);
6370 &image->planes[stencil_plane].primary_surface;
6372 anv_image_address(image, &stencil_surface->memory_range);
6376 info.stencil_aux_usage = image->planes[stencil_plane].aux_usage;
6430 info.surf = &fsr_iview->image->planes[0].primary_surface.isl;
6434 fsr_iview->image->bindings[0].address.bo,
6435 fsr_iview->image->bindings[0].address.offset +
6436 fsr_iview->image->bindings[0].memory_range.offset);
6438 anv_mocs(device, fsr_iview->image->bindings[0].address.bo,
6520 assert(gfx->samples == 0 || gfx->samples == iview->vk.image->samples);
6521 gfx->samples |= iview->vk.image->samples;
6525 iview->image,
6551 transition_color_buffer(cmd_buffer, iview->image,
6562 transition_color_buffer(cmd_buffer, iview->image,
6584 if (iview->image->vk.samples == 1) {
6585 anv_image_ccs_op(cmd_buffer, iview->image,
6593 anv_image_mcs_op(cmd_buffer, iview->image,
6607 /* This image has the auxiliary buffer enabled. We can mark the
6612 set_image_fast_clear_state(cmd_buffer, iview->image,
6616 set_image_fast_clear_state(cmd_buffer, iview->image,
6624 anv_image_clear_color(cmd_buffer, iview->image,
6634 anv_image_clear_color(cmd_buffer, iview->image,
6663 iview->image,
6677 iview->image->planes[0].aux_usage != ISL_AUX_USAGE_NONE &&
6682 iview->image,
6725 d_iview->image,
6738 s_iview->image,
6758 assert(gfx->samples == 0 || gfx->samples == ds_iview->vk.image->samples);
6759 gfx->samples |= ds_iview->vk.image->samples;
6783 transition_depth_buffer(cmd_buffer, d_iview->image,
6790 transition_depth_buffer(cmd_buffer, d_iview->image,
6805 transition_stencil_buffer(cmd_buffer, s_iview->image,
6814 transition_stencil_buffer(cmd_buffer, s_iview->image,
6833 anv_image_hiz_clear(cmd_buffer, ds_iview->image,
6839 anv_image_clear_depth_stencil(cmd_buffer, ds_iview->image,
6854 anv_image_hiz_clear(cmd_buffer, ds_iview->image,
6860 anv_image_clear_depth_stencil(cmd_buffer, ds_iview->image,
6973 genX(cmd_buffer_mark_image_written)(cmd_buffer, iview->image,
6986 genX(cmd_buffer_mark_image_written)(cmd_buffer, iview->image,
7022 src_iview->image, aspect,
7028 dst_iview->image, aspect,
7037 src_iview->image, src_aux_usage,
7040 dst_iview->image, dst_aux_usage,
7055 src_iview->image, src_aux_usage,
7058 dst_iview->image, dst_aux_usage,
7149 transition_depth_buffer(cmd_buffer, src_iview->image,
7164 transition_depth_buffer(cmd_buffer, src_iview->image,
7199 const struct anv_image *image = iview->image;
7201 anv_image_aspect_to_plane(image, VK_IMAGE_ASPECT_STENCIL_BIT);
7203 if (anv_surface_is_valid(&image->planes[plane].shadow_surface) &&
7206 anv_image_copy_to_shadow(cmd_buffer, image,