Lines Matching defs:device
100 struct anv_device *device = cmd_buffer->device;
101 uint32_t mocs = isl_mocs(&device->isl_dev, 0, false);
162 (struct anv_address) { device->dynamic_state_pool.block_pool.bo, 0 };
171 (struct anv_address) { device->instruction_state_pool.block_pool.bo, 0 };
182 if (anv_use_relocations(device->physical)) {
216 (struct anv_address) { device->surface_state_pool.block_pool.bo, 0 };
312 if (anv_use_relocations(cmd_buffer->device->physical)) {
313 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
332 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
383 anv_can_fast_clear_color_view(struct anv_device * device,
400 anv_layout_to_fast_clear_type(&device->info, iview->image,
469 anv_can_hiz_clear_ds_view(struct anv_device *device,
489 anv_layout_to_aux_usage(&device->info, iview->image,
493 if (!blorp_can_hiz_clear_depth(&device->info,
513 if (GFX_VER == 8 && anv_can_sample_with_hiz(&device->info, iview->image))
550 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
597 aux_entry_map = intel_aux_map_get_entry(cmd_buffer->device->aux_map_ctx,
600 assert(!anv_use_relocations(cmd_buffer->device->physical));
643 cmd_buffer->device->physical->has_implicit_ccs &&
644 cmd_buffer->device->info.has_aux_map) {
659 anv_layout_to_aux_state(&cmd_buffer->device->info, image,
663 anv_layout_to_aux_state(&cmd_buffer->device->info, image,
752 cmd_buffer->device->physical->has_implicit_ccs &&
753 cmd_buffer->device->info.has_aux_map) {
812 sdi.Address = anv_image_get_compression_state_addr(cmd_buffer->device,
827 sdi.Address = anv_image_get_fast_clear_type_addr(cmd_buffer->device,
852 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
855 mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer->device,
868 mi_mem32(anv_image_get_compression_state_addr(cmd_buffer->device,
935 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
938 mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer->device,
1066 anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect);
1069 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
1116 .bo = cmd_buffer->device->surface_state_pool.block_pool.bo,
1118 cmd_buffer->device->isl_dev.ss.clear_value_offset,
1121 anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect);
1122 unsigned copy_size = cmd_buffer->device->isl_dev.ss.clear_value_size;
1149 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
1196 struct anv_device *device = cmd_buffer->device;
1197 const struct intel_device_info *devinfo = &device->info;
1332 if (device->physical->has_implicit_ccs && devinfo->has_aux_map) {
1339 assert(!(device->physical->has_implicit_ccs && devinfo->has_aux_map));
1570 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
1680 if (cmd_buffer->device->info.has_aux_map) {
1737 * default locations emitted at the device initialization might have been
1742 if (cmd_buffer->device->vk.enabled_extensions.EXT_sample_locations &&
1878 mi_builder_init(&b, &primary->device->info, &primary->batch);
1892 primary->device->surface_state_pool.block_pool.bo;
1968 assert(cfg == cmd_buffer->device->l3_config);
2019 genX(emit_l3_config)(&cmd_buffer->batch, cmd_buffer->device, cfg);
2026 struct anv_device *device,
2172 pipe.Address = device->workaround_address;
2243 lrm.MemoryAddress = device->workaround_address;
2305 pipe.Address = device->workaround_address;
2311 if ((bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT) && device->info.has_aux_map) {
2345 if (unlikely(cmd_buffer->device->physical->always_flush_cache))
2369 cmd_buffer->device,
2469 anv_pipe_flush_bits_for_access_flags(cmd_buffer->device, src_flags) |
2470 anv_pipe_invalidate_bits_for_access_flags(cmd_buffer->device, dst_flags);
2503 cmd_buffer->device->info.max_constant_urb_size_kb;
2541 if (intel_device_info_is_dg2(&cmd_buffer->device->info)) {
2545 c.MOCS = anv_mocs(cmd_buffer->device, NULL, 0);
2590 anv_use_relocations(cmd_buffer->device->physical);
2622 .bo = cmd_buffer->device->instruction_state_pool.block_pool.bo,
2629 anv_isl_format_for_descriptor_type(cmd_buffer->device,
2631 anv_fill_buffer_surface_state(cmd_buffer->device, surface_state,
2650 anv_isl_format_for_descriptor_type(cmd_buffer->device,
2652 anv_fill_buffer_surface_state(cmd_buffer->device, surface_state,
2722 surface_state = cmd_buffer->device->null_surface_state;
2740 vk_debug_report(&cmd_buffer->device->physical->instance->vk,
2752 surface_state = cmd_buffer->device->null_surface_state;
2767 surface_state = cmd_buffer->device->null_surface_state;
2780 surface_state = cmd_buffer->device->null_surface_state;
2806 anv_isl_format_for_descriptor_type(cmd_buffer->device,
2814 anv_fill_buffer_surface_state(cmd_buffer->device, surface_state,
2820 surface_state = cmd_buffer->device->null_surface_state;
2836 surface_state = cmd_buffer->device->null_surface_state;
3035 .bo = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
3042 .bo = cmd_buffer->device->instruction_state_pool.block_pool.bo,
3075 .bo = cmd_buffer->device->workaround_bo,
3174 UNUSED uint32_t mocs = anv_mocs(cmd_buffer->device, NULL, 0);
3242 cmd_buffer->device->dynamic_state_pool.block_pool.bo);
3265 c.MOCS = isl_mocs(&cmd_buffer->device->isl_dev, 0, false);
3295 .MOCS = isl_mocs(&cmd_buffer->device->isl_dev, 0, false));
3323 if (cmd_buffer->device->robust_buffer_access) {
3844 .MOCS = anv_mocs(cmd_buffer->device, buffer->address.bo,
3873 .MOCS = anv_mocs(cmd_buffer->device, NULL,
3907 if (intel_device_info_is_dg2(&cmd_buffer->device->info)) {
3928 sob.MOCS = anv_mocs(cmd_buffer->device, xfb->buffer->address.bo, 0);
3946 sob.MOCS = anv_mocs(cmd_buffer->device, NULL, 0);
3951 if (intel_device_info_is_dg2(&cmd_buffer->device->info)) {
3990 pc.Address = cmd_buffer->device->workaround_address;
4086 .MOCS = anv_mocs(cmd_buffer->device, addr.bo,
4126 .bo = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
4143 .bo = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
4501 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
4538 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
4818 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
4886 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
5127 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
5167 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
5284 verify_cmd_parser(const struct anv_device *device,
5288 if (device->physical->cmd_parser_version < required_version) {
5289 return vk_errorf(device->physical, VK_ERROR_FEATURE_NOT_PRESENT,
5343 const struct intel_device_info *devinfo = &pipeline->base.device->info;
5360 cw.PostSync.MOCS = anv_mocs(pipeline->base.device, NULL, 0);
5390 const struct intel_device_info *devinfo = &pipeline->base.device->info;
5465 .bo = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
5507 if (verify_cmd_parser(cmd_buffer->device, 5,
5528 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
5598 struct anv_device *device = cmd_buffer->device;
5608 brw_rt_compute_scratch_layout(&layout, &device->info,
5616 .bo = device->ray_query_bo,
5617 .offset = device->ray_query_bo->size
5723 anv_shader_bin_get_bsr(cmd_buffer->device->rt_trivial_return, 0),
5745 .bo = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
5761 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
5827 cw.PostSync.MOCS = anv_mocs(pipeline->base.device, NULL, 0);
5830 struct anv_device *device = cmd_buffer->device;
5834 .KernelStartPointer = device->rt_trampoline->kernel.offset,
5907 UNUSED const struct intel_device_info *devinfo = &cmd_buffer->device->info;
6132 anv_use_relocations(cmd_buffer->device->physical))
6163 anv_use_relocations(cmd_buffer->device->physical))
6218 const struct intel_device_info *devinfo = &cmd_buffer->device->info;
6289 struct anv_device *device = cmd_buffer->device;
6297 device->isl_dev.ds.size / 4);
6304 .mocs = anv_mocs(device, NULL, ISL_SURF_USAGE_DEPTH_BIT),
6338 dw + device->isl_dev.ds.depth_offset / 4,
6341 anv_mocs(device, depth_address.bo, ISL_SURF_USAGE_DEPTH_BIT);
6356 dw + device->isl_dev.ds.hiz_offset / 4,
6379 dw + device->isl_dev.ds.stencil_offset / 4,
6382 anv_mocs(device, stencil_address.bo, ISL_SURF_USAGE_STENCIL_BIT);
6385 isl_emit_depth_stencil_hiz_s(&device->isl_dev, dw, &info);
6405 pc.Address = cmd_buffer->device->workaround_address;
6416 struct anv_device *device = cmd_buffer->device;
6418 if (!device->vk.enabled_extensions.KHR_fragment_shading_rate)
6422 device->isl_dev.cpb.size / 4);
6433 dw + device->isl_dev.cpb.offset / 4,
6438 anv_mocs(device, fsr_iview->image->bindings[0].address.bo,
6442 isl_emit_cpb_control_s(&device->isl_dev, dw, &info);
6524 anv_layout_to_aux_usage(&cmd_buffer->device->info,
6541 anv_can_fast_clear_color_view(cmd_buffer->device, iview,
6662 anv_image_fill_surface_state(cmd_buffer->device,
6724 anv_layout_to_aux_usage(&cmd_buffer->device->info,
6737 anv_layout_to_aux_usage(&cmd_buffer->device->info,
6771 anv_can_hiz_clear_ds_view(cmd_buffer->device, d_iview,
6906 isl_null_fill_state(&cmd_buffer->device->isl_dev,
6914 isl_null_fill_state(&cmd_buffer->device->isl_dev,
7021 anv_layout_to_aux_usage(&cmd_buffer->device->info,
7027 anv_layout_to_aux_usage(&cmd_buffer->device->info,
7229 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
7262 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
7334 cmd_buffer->device->dynamic_state_pool.block_pool.bo,
7362 cmd_buffer->device->dynamic_state_pool.block_pool.bo,
7387 cmd_buffer->device->dynamic_state_pool.block_pool.bo,
7500 struct anv_device *device,
7511 mi_builder_init(&b, &device->info, batch);