Lines Matching defs:bits
61 enum anv_pipe_bits bits = 0;
62 bits |= (pc->DepthCacheFlushEnable) ? ANV_PIPE_DEPTH_CACHE_FLUSH_BIT : 0;
63 bits |= (pc->DCFlushEnable) ? ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0;
65 bits |= (pc->PSSStallSyncEnable) ? ANV_PIPE_PSS_STALL_SYNC_BIT : 0;
68 bits |= (pc->TileCacheFlushEnable) ? ANV_PIPE_TILE_CACHE_FLUSH_BIT : 0;
69 bits |= (pc->HDCPipelineFlushEnable) ? ANV_PIPE_HDC_PIPELINE_FLUSH_BIT : 0;
71 bits |= (pc->RenderTargetCacheFlushEnable) ? ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT : 0;
72 bits |= (pc->VFCacheInvalidationEnable) ? ANV_PIPE_VF_CACHE_INVALIDATE_BIT : 0;
73 bits |= (pc->StateCacheInvalidationEnable) ? ANV_PIPE_STATE_CACHE_INVALIDATE_BIT : 0;
74 bits |= (pc->ConstantCacheInvalidationEnable) ? ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT : 0;
75 bits |= (pc->TextureCacheInvalidationEnable) ? ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT : 0;
76 bits |= (pc->InstructionCacheInvalidateEnable) ? ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT : 0;
77 bits |= (pc->StallAtPixelScoreboard) ? ANV_PIPE_STALL_AT_SCOREBOARD_BIT : 0;
78 bits |= (pc->DepthStallEnable) ? ANV_PIPE_DEPTH_STALL_BIT : 0;
79 bits |= (pc->CommandStreamerStallEnable) ? ANV_PIPE_CS_STALL_BIT : 0;
80 return bits;
1377 * with the MCS referring to an invalid plane because not all bits of
2028 enum anv_pipe_bits bits)
2044 * Exercising the write cache flush bits (Render Target Cache Flush
2057 if (bits & ANV_PIPE_FLUSH_BITS)
2058 bits |= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
2067 if (GFX_VER == 12 && (bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT))
2068 bits |= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
2073 if ((bits & ANV_PIPE_INVALIDATE_BITS) &&
2074 (bits & ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT)) {
2075 bits |= ANV_PIPE_END_OF_PIPE_SYNC_BIT;
2076 bits &= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
2088 if (bits & ANV_PIPE_POST_SYNC_BIT) {
2090 bits |= ANV_PIPE_CS_STALL_BIT;
2091 bits &= ~ANV_PIPE_POST_SYNC_BIT;
2094 if (bits & (ANV_PIPE_FLUSH_BITS | ANV_PIPE_STALL_BITS |
2098 pipe.TileCacheFlushEnable = bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT;
2099 pipe.HDCPipelineFlushEnable |= bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
2102 pipe.DCFlushEnable |= bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
2104 pipe.DepthCacheFlushEnable = bits & ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
2105 pipe.DCFlushEnable |= bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT;
2107 bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
2114 pipe.DepthCacheFlushEnable || (bits & ANV_PIPE_DEPTH_STALL_BIT);
2116 pipe.DepthStallEnable = bits & ANV_PIPE_DEPTH_STALL_BIT;
2120 pipe.PSSStallSyncEnable = bits & ANV_PIPE_PSS_STALL_SYNC_BIT;
2123 pipe.CommandStreamerStallEnable = bits & ANV_PIPE_CS_STALL_BIT;
2130 * when only Read Only Cache Invalidation bits are set (State
2142 pipe.StallAtPixelScoreboard = bits & ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
2165 * Immediate Data, Required Write Cache Flush bits set)
2169 if (bits & ANV_PIPE_END_OF_PIPE_SYNC_BIT) {
2204 if (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
2205 bits &= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES);
2221 * Immediate Data, Required Write Cache Flush bits set)
2247 bits &= ~(ANV_PIPE_FLUSH_BITS | ANV_PIPE_STALL_BITS |
2251 if (bits & ANV_PIPE_INVALIDATE_BITS) {
2262 if (GFX_VER == 9 && (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT))
2267 bits & ANV_PIPE_STATE_CACHE_INVALIDATE_BIT;
2269 bits & ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
2275 bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
2278 bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
2280 bits & ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
2282 bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT;
2311 if ((bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT) && device->info.has_aux_map) {
2319 bits &= ~ANV_PIPE_INVALIDATE_BITS;
2322 return bits;
2343 enum anv_pipe_bits bits = cmd_buffer->state.pending_pipe_bits;
2346 bits |= ANV_PIPE_FLUSH_BITS | ANV_PIPE_INVALIDATE_BITS;
2347 else if (bits == 0)
2351 (bits & (ANV_PIPE_FLUSH_BITS | ANV_PIPE_STALL_BITS | ANV_PIPE_INVALIDATE_BITS)) != 0;
2356 (bits & ANV_PIPE_CS_STALL_BIT) &&
2357 (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT)) {
2371 bits);
2387 trace_intel_end_stall(&cmd_buffer->trace, bits,
2468 enum anv_pipe_bits bits =
2472 anv_add_pending_pipe_bits(cmd_buffer, bits, reason);
3408 * contains only 5 bits, so we can only use it for buffers smaller than
5209 * the only bits that are changed are scoreboard related: Scoreboard
6399 * the surface state bits of this state is changing).
7296 /* Set of stage bits for which are pipelined, i.e. they get queued