Lines Matching defs:batch
109 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
114 &cmd_buffer->batch, GENX(3DSTATE_BINDING_TABLE_POOL_ALLOC), btpa) {
128 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
149 anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) {
283 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
325 anv_batch_set_error(&cmd_buffer->batch, result);
346 anv_batch_set_error(&cmd_buffer->batch, result);
359 anv_batch_set_error(&cmd_buffer->batch, result);
550 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
811 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
826 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
852 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
917 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
935 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
960 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
1074 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
1081 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
1149 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
1576 return anv_batch_set_error(&cmd_buffer->batch,
1736 /* Emit the sample pattern at the beginning of the batch because the
1744 genX(emit_sample_pattern)(&cmd_buffer->batch, NULL);
1783 * the end of the previous batch buffer. This has been fine so far since
1802 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1807 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1820 if (anv_batch_has_error(&cmd_buffer->batch))
1821 return cmd_buffer->batch.status;
1851 if (anv_batch_has_error(&primary->batch))
1868 assert(!anv_batch_has_error(&secondary->batch));
1878 mi_builder_init(&b, &primary->device->info, &primary->batch);
1979 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
2000 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
2012 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
2019 genX(emit_l3_config)(&cmd_buffer->batch, cmd_buffer->device, cfg);
2025 genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
2096 anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe) {
2241 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
2263 anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe);
2265 anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe) {
2312 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
2368 genX(emit_apply_pipe_flushes)(&cmd_buffer->batch,
2376 anv_batch_write_reg(&cmd_buffer->batch, GENX(COMMON_SLICE_CHICKEN1), c1) {
2519 anv_batch_emit(&cmd_buffer->batch,
2528 anv_batch_emit(&cmd_buffer->batch,
2542 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_ALL), c) {
2954 anv_batch_set_error(&cmd_buffer->batch, result);
2960 anv_batch_set_error(&cmd_buffer->batch, result);
2995 anv_batch_emit(&cmd_buffer->batch,
3004 anv_batch_emit(&cmd_buffer->batch,
3176 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS), c) {
3263 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_ALL), c) {
3291 dw = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
3300 &cmd_buffer->batch, dw + 2 + i * 2,
3443 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_TASK_SHADER_DATA), data) {
3466 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_MESH_SHADER_DATA), data) {
3538 anv_batch_emit_merge(&cmd_buffer->batch, dwords,
3639 anv_batch_emit(&cmd_buffer->batch,
3675 anv_batch_emit(&cmd_buffer->batch,
3764 anv_batch_emit(&cmd_buffer->batch,
3790 anv_batch_emit_merge(&cmd_buffer->batch, dwords, streamout_state_dw);
3823 p = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
3884 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, &p[1 + i * 4], &state);
3919 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SO_BUFFER), sob) {
3966 anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->base.batch);
3987 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
4064 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_TOPOLOGY), vft) {
4078 uint32_t *p = anv_batch_emitn(&cmd_buffer->batch, 5,
4081 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, p + 1,
4205 if (anv_batch_has_error(&cmd_buffer->batch))
4224 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
4253 if (anv_batch_has_error(&cmd_buffer->batch))
4274 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
4304 if (anv_batch_has_error(&cmd_buffer->batch))
4322 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
4352 if (anv_batch_has_error(&cmd_buffer->batch))
4388 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
4411 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
4430 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
4475 if (anv_batch_has_error(&cmd_buffer->batch))
4501 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
4516 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
4538 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
4582 if (anv_batch_has_error(&cmd_buffer->batch))
4612 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
4639 if (anv_batch_has_error(&cmd_buffer->batch))
4670 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
4721 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
4734 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
4763 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
4806 if (anv_batch_has_error(&cmd_buffer->batch))
4818 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
4841 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
4874 if (anv_batch_has_error(&cmd_buffer->batch))
4886 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
4910 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
4966 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
4972 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
5021 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), srm) {
5042 if (anv_batch_has_error(&cmd_buffer->batch))
5056 anv_batch_emit(&cmd_buffer->batch, GENX(3DMESH_1D), m) {
5088 emit_indirect_3dmesh_1d(struct anv_batch *batch,
5093 uint32_t *dw = anv_batch_emitn(batch, len, GENX(3DMESH_1D),
5116 if (anv_batch_has_error(&cmd_buffer->batch))
5127 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
5134 emit_indirect_3dmesh_1d(&cmd_buffer->batch,
5158 if (anv_batch_has_error(&cmd_buffer->batch))
5167 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
5180 emit_indirect_3dmesh_1d(&cmd_buffer->batch, true, uses_drawid);
5219 anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->base.batch);
5252 anv_batch_emit(&cmd_buffer->batch,
5266 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD), curbe) {
5305 if (anv_batch_has_error(&cmd_buffer->batch))
5347 anv_batch_emit(&cmd_buffer->batch, GENX(COMPUTE_WALKER), cw) {
5394 anv_batch_emit(&cmd_buffer->batch, GENX(GPGPU_WALKER), ggw) {
5408 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_STATE_FLUSH), msf);
5445 if (anv_batch_has_error(&cmd_buffer->batch))
5499 UNUSED struct anv_batch *batch = &cmd_buffer->batch;
5528 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
5542 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
5550 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
5558 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
5565 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
5576 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
5686 if (anv_batch_has_error(&cmd_buffer->batch))
5706 anv_reloc_list_add_bo(cmd_buffer->batch.relocs,
5707 cmd_buffer->batch.alloc,
5761 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
5815 anv_batch_emit(&cmd_buffer->batch, GENX(COMPUTE_WALKER), cw) {
5923 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), t);
5934 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_VFE_STATE), vfe) {
5975 anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) {
5992 anv_batch_write_reg(&cmd_buffer->batch, GENX(SLICE_COMMON_ECO_CHICKEN1), scec1) {
6033 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
6037 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
6044 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
6087 anv_batch_write_reg(&cmd_buffer->batch, GENX(COMMON_SLICE_CHICKEN1), reg) {
6274 anv_batch_write_reg(&cmd_buffer->batch, GENX(GT_MODE), gt) {
6296 uint32_t *dw = anv_batch_emit_dwords(&cmd_buffer->batch,
6337 anv_batch_emit_reloc(&cmd_buffer->batch,
6355 anv_batch_emit_reloc(&cmd_buffer->batch,
6378 anv_batch_emit_reloc(&cmd_buffer->batch,
6403 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
6421 uint32_t *dw = anv_batch_emit_dwords(&cmd_buffer->batch,
6432 anv_batch_emit_reloc(&cmd_buffer->batch,
6468 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_UNKNOWN);
7077 if (anv_batch_has_error(&cmd_buffer->batch))
7229 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
7235 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
7262 mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
7325 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
7353 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
7382 anv_batch_emit(&cmd_buffer->batch, GENX(MI_SEMAPHORE_WAIT), sem) {
7453 anv_batch_write_reg(&cmd_buffer->batch, GENX(CS_DEBUG_MODE2), csdm2) {
7460 anv_batch_write_reg(&cmd_buffer->batch, GENX(INSTPM), instpm) {
7499 void genX(cmd_emit_timestamp)(struct anv_batch *batch,
7504 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
7511 mi_builder_init(&b, &device->info, batch);