Lines Matching refs:base
184 vk_object_base_init(&device->vk, &pipeline->base,
218 vk_object_base_finish(&pipeline->base);
322 populate_base_prog_key(device, robust_buffer_acccess, &key->base);
337 populate_base_prog_key(device, robust_buffer_acccess, &key->base);
349 populate_base_prog_key(device, robust_buffer_acccess, &key->base);
359 populate_base_prog_key(device, robust_buffer_acccess, &key->base);
421 populate_base_prog_key(device, robust_buffer_access, &key->base);
431 populate_base_prog_key(device, robust_buffer_access, &key->base);
443 const struct anv_device *device = pipeline->base.device;
447 populate_base_prog_key(device, robust_buffer_acccess, &key->base);
501 populate_base_prog_key(device, robust_buffer_acccess, &key->base);
511 populate_base_prog_key(device, robust_buffer_access, &key->base);
562 const bool rba = pipeline->base.device->robust_buffer_access;
588 const struct anv_device *device = pipeline->base.device;
615 const bool rba = pipeline->base.device->robust_buffer_access;
637 const bool rba = pipeline->base.device->robust_buffer_access;
699 struct brw_stage_prog_data *prog_data = &stage->prog_data.base;
818 &vs_stage->prog_data.vs.base.vue_map,
830 .log_data = pipeline->base.device,
955 .input_vue_map = &tcs_stage->prog_data.tcs.base.vue_map,
980 &gs_stage->prog_data.gs.base.vue_map,
1327 const struct anv_device *device = pipeline->base.device;
1331 pipeline->base.device->robust_buffer_access,
1336 pipeline->base.device->robust_buffer_access,
1342 pipeline->base.device->robust_buffer_access,
1347 pipeline->base.device->robust_buffer_access,
1352 pipeline->base.device->robust_buffer_access,
1359 pipeline->base.device->robust_buffer_access,
1364 pipeline->base.device->robust_buffer_access,
1395 anv_device_search_for_kernel(pipeline->base.device, cache,
1421 anv_pipeline_add_executables(&pipeline->base, &stages[s],
1433 vk_perf(VK_LOG_OBJS(cache ? &cache->base :
1434 &pipeline->base.device->vk.base),
1446 anv_shader_bin_unref(pipeline->base.device, pipeline->shaders[s]);
1488 stages[s].nir = anv_pipeline_stage_get_nir(&pipeline->base, cache,
1515 const struct brw_compiler *compiler = pipeline->base.device->physical->compiler;
1537 (pipeline->base.flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR);
1592 if (pipeline->base.device->info.ver >= 12 &&
1619 anv_pipeline_lower_nir(&pipeline->base, stage_ctx, &stages[s], layout);
1645 const struct intel_device_info *devinfo = &pipeline->base.device->info;
1685 anv_pipeline_compile_tcs(compiler, stage_ctx, pipeline->base.device,
1689 anv_pipeline_compile_tes(compiler, stage_ctx, pipeline->base.device,
1693 anv_pipeline_compile_gs(compiler, stage_ctx, pipeline->base.device,
1697 anv_pipeline_compile_task(compiler, stage_ctx, pipeline->base.device,
1701 anv_pipeline_compile_mesh(compiler, stage_ctx, pipeline->base.device,
1705 anv_pipeline_compile_fs(compiler, stage_ctx, pipeline->base.device,
1713 result = vk_error(pipeline->base.device, VK_ERROR_OUT_OF_HOST_MEMORY);
1717 anv_nir_validate_push_layout(&stages[s].prog_data.base,
1721 anv_device_upload_kernel(pipeline->base.device, cache, s,
1725 stages[s].prog_data.base.program_size,
1726 &stages[s].prog_data.base,
1737 anv_pipeline_add_executables(&pipeline->base, &stages[s], bin);
1773 anv_shader_bin_unref(pipeline->base.device, pipeline->shaders[s]);
1792 struct anv_device *device = pipeline->base.device;
1814 (pipeline->base.flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR);
1845 stage.nir = anv_pipeline_stage_get_nir(&pipeline->base, cache, mem_ctx, &stage);
1853 anv_pipeline_lower_nir(&pipeline->base, mem_ctx, &stage, layout);
1895 anv_nir_validate_push_layout(&stage.prog_data.base, &stage.bind_map);
1903 const unsigned code_size = stage.prog_data.base.program_size;
1908 &stage.prog_data.base,
1920 anv_pipeline_add_executables(&pipeline->base, &stage, bin);
1965 result = anv_pipeline_init(&pipeline->base, device,
1973 anv_batch_set_storage(&pipeline->base.batch, ANV_NULL_ADDRESS,
1978 anv_pipeline_finish(&pipeline->base, device, pAllocator);
1985 *pPipeline = anv_pipeline_to_handle(&pipeline->base);
1987 return pipeline->base.batch.status;
2059 result = anv_pipeline_init(&pipeline->base, device,
2065 anv_batch_set_storage(&pipeline->base.batch, ANV_NULL_ADDRESS,
2087 anv_pipeline_finish(&pipeline->base, device, alloc);
2091 anv_pipeline_setup_l3_config(&pipeline->base, false);
2188 *pPipeline = anv_pipeline_to_handle(&pipeline->base);
2190 return pipeline->base.batch.status;
2244 pipeline->base.device->physical->compiler;
2271 .log_data = pipeline->base.device,
2281 const unsigned code_size = stage->prog_data.base.program_size;
2283 anv_device_upload_kernel(pipeline->base.device,
2288 &stage->prog_data.base,
2296 anv_pipeline_add_executables(&pipeline->base, stage, bin);
2393 populate_bs_prog_key(pipeline->base.device,
2394 pipeline->base.device->robust_buffer_access,
2455 stages[i].bin = anv_device_search_for_kernel(pipeline->base.device, cache,
2466 anv_pipeline_add_executables(&pipeline->base, &stages[i], stages[i].bin);
2486 const struct intel_device_info *devinfo = &pipeline->base.device->info;
2502 (pipeline->base.flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR);
2524 stages[i].nir = anv_pipeline_stage_get_nir(&pipeline->base, cache,
2531 anv_pipeline_lower_nir(&pipeline->base, pipeline_ctx, &stages[i], layout);
2717 .base.nr_params = 4,
2718 .base.param = dummy_params,
2736 trampoline_prog_data.base.program_size,
2737 &trampoline_prog_data.base,
2788 return_data, return_prog_data.base.program_size,
2789 &return_prog_data.base, sizeof(return_prog_data),
2822 util_dynarray_init(&pipeline->shaders, pipeline->base.mem_ctx);
2828 anv_pipeline_setup_l3_config(&pipeline->base, /* needs_slm */ false);
2873 result = anv_pipeline_init(&pipeline->base, device,
2933 anv_pipeline_finish(&pipeline->base, device, pAllocator);
2940 *pPipeline = anv_pipeline_to_handle(&pipeline->base);
2942 return pipeline->base.batch.status;