Lines Matching defs:nir
39 #include "nir/nir_xfb_info.h"
49 * we can't do that yet because we don't have the ability to copy nir.
135 nir_shader *nir;
139 mem_ctx, &nir);
146 nir_print_shader(nir, stderr);
149 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
150 nir_shader_get_entrypoint(nir), true, false);
155 NIR_PASS(_, nir, nir_lower_sysvals_to_varyings, &sysvals_to_varyings);
161 NIR_PASS(_, nir, nir_opt_access, &opt_access_options);
163 NIR_PASS(_, nir, nir_lower_frexp);
166 nir->info.separate_shader = true;
168 brw_preprocess_nir(compiler, nir, NULL);
170 return nir;
528 nir_shader *nir;
658 nir_shader *nir;
660 nir = anv_device_search_for_nir(pipeline->device, cache,
664 if (nir) {
665 assert(nir->info.stage == stage->stage);
666 return nir;
669 nir = anv_shader_stage_to_nir(pipeline->device, stage->info, mem_ctx);
670 if (nir) {
671 anv_device_upload_nir(pipeline->device, cache, nir, stage->shader_sha1);
672 return nir;
700 nir_shader *nir = stage->nir;
702 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
703 NIR_PASS(_, nir, nir_lower_wpos_center);
704 NIR_PASS(_, nir, nir_lower_input_attachments,
711 NIR_PASS(_, nir, anv_nir_lower_ycbcr_textures, layout);
714 NIR_PASS(_, nir, anv_nir_lower_multiview,
718 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
720 NIR_PASS(_, nir, brw_nir_lower_storage_image, compiler->devinfo);
722 NIR_PASS(_, nir, nir_lower_explicit_io, nir_var_mem_global,
724 NIR_PASS(_, nir, nir_lower_explicit_io, nir_var_mem_push_const,
727 NIR_PASS(_, nir, brw_nir_lower_ray_queries, &pdevice->info);
730 NIR_PASS_V(nir, anv_nir_apply_pipeline_layout,
734 NIR_PASS(_, nir, nir_lower_explicit_io, nir_var_mem_ubo,
737 NIR_PASS(_, nir, nir_lower_explicit_io, nir_var_mem_ssbo,
745 NIR_PASS(_, nir, nir_copy_prop);
746 NIR_PASS(_, nir, nir_opt_constant_folding);
748 NIR_PASS(_, nir, anv_nir_lower_ubo_loads);
753 NIR_PASS(_, nir, nir_lower_non_uniform_access,
760 NIR_PASS_V(nir, anv_nir_compute_push_layout,
764 if (gl_shader_stage_uses_workgroup(nir->info.stage)) {
765 if (!nir->info.shared_memory_explicit_layout) {
766 NIR_PASS(_, nir, nir_lower_vars_to_explicit_types,
770 NIR_PASS(_, nir, nir_lower_explicit_io,
773 if (nir->info.zero_initialize_shared_memory &&
774 nir->info.shared_size > 0) {
780 const unsigned shared_size = ALIGN(nir->info.shared_size, chunk_size);
782 intel_calculate_slm_size(compiler->devinfo->ver, nir->info.shared_size));
784 NIR_PASS(_, nir, nir_zero_initialize_shared_memory,
789 if (gl_shader_stage_is_compute(nir->info.stage) ||
790 gl_shader_stage_is_mesh(nir->info.stage))
791 NIR_PASS(_, nir, brw_nir_lower_cs_intrinsics);
793 stage->nir = nir;
802 brw_nir_link_shaders(compiler, vs_stage->nir, next_stage->nir);
819 vs_stage->nir->info.outputs_written,
820 vs_stage->nir->info.separate_shader,
826 .nir = vs_stage->nir,
882 brw_nir_link_shaders(compiler, tcs_stage->nir, tes_stage->nir);
884 nir_lower_patch_vertices(tes_stage->nir,
885 tcs_stage->nir->info.tess.tcs_vertices_out,
889 merge_tess_info(&tes_stage->nir->info, &tcs_stage->nir->info);
896 tes_stage->nir->info.tess._primitive_mode;
899 tes_stage->nir->info.tess._primitive_mode == TESS_PRIMITIVE_QUADS &&
900 tes_stage->nir->info.tess.spacing == TESS_SPACING_EQUAL;
911 tcs_stage->nir->info.outputs_written;
913 tcs_stage->nir->info.patch_outputs_written;
918 .nir = tcs_stage->nir,
934 brw_nir_link_shaders(compiler, tes_stage->nir, next_stage->nir);
945 tcs_stage->nir->info.outputs_written;
947 tcs_stage->nir->info.patch_outputs_written;
952 .nir = tes_stage->nir,
969 brw_nir_link_shaders(compiler, gs_stage->nir, next_stage->nir);
981 gs_stage->nir->info.outputs_written,
982 gs_stage->nir->info.separate_shader, 1);
987 .nir = gs_stage->nir,
1004 brw_nir_link_shaders(compiler, task_stage->nir, next_stage->nir);
1016 .nir = task_stage->nir,
1032 brw_nir_link_shaders(compiler, mesh_stage->nir, next_stage->nir);
1046 .nir = mesh_stage->nir,
1072 nir_foreach_shader_out_variable_safe(var, stage->nir) {
1136 .nir = fs_stage->nir,
1166 char *nir = NULL;
1167 if (stage->nir &&
1170 nir = nir_shader_as_str(stage->nir, pipeline->mem_ctx);
1250 .nir = nir,
1488 stages[s].nir = anv_pipeline_stage_get_nir(&pipeline->base, cache,
1491 if (stages[s].nir == NULL) {
1601 shaders[s] = stages[s].nir;
1622 prev_stage->nir->info.outputs_written |= stages[s].nir->info.inputs_read &
1624 stages[s].nir->info.inputs_read |= prev_stage->nir->info.outputs_written &
1626 prev_stage->nir->info.patch_outputs_written |= stages[s].nir->info.patch_inputs_read;
1627 stages[s].nir->info.patch_inputs_read |= prev_stage->nir->info.patch_outputs_written;
1649 !stages[MESA_SHADER_FRAGMENT].nir->info.fs.uses_sample_shading &&
1666 last_psr->nir->info.outputs_written |= VARYING_BIT_PRIMITIVE_SHADING_RATE;
1729 stages[s].nir->xfb_info,
1845 stage.nir = anv_pipeline_stage_get_nir(&pipeline->base, cache, mem_ctx, &stage);
1846 if (stage.nir == NULL) {
1851 NIR_PASS(_, stage.nir, anv_nir_add_base_work_group_id);
1855 unsigned local_size = stage.nir->info.workgroup_size[0] *
1856 stage.nir->info.workgroup_size[1] *
1857 stage.nir->info.workgroup_size[2];
1864 stage.nir->info.cs.uses_wide_subgroup_intrinsics &&
1865 stage.nir->info.subgroup_size == SUBGROUP_SIZE_API_CONSTANT &&
1868 stage.nir->info.subgroup_size = SUBGROUP_SIZE_FULL_SUBGROUPS;
1876 if (stage.nir->info.subgroup_size == SUBGROUP_SIZE_FULL_SUBGROUPS)
1877 stage.nir->info.subgroup_size = BRW_SUBGROUP_SIZE;
1882 .nir = stage.nir,
2238 nir_shader *nir,
2249 if (nir->info.stage != MESA_SHADER_COMPUTE) {
2250 NIR_PASS(_, nir, nir_lower_shader_calls,
2254 NIR_PASS(_, nir, brw_nir_lower_shader_calls);
2255 NIR_PASS_V(nir, brw_nir_lower_rt_intrinsics, devinfo);
2264 .nir = nir,
2524 stages[i].nir = anv_pipeline_stage_get_nir(&pipeline->base, cache,
2526 if (stages[i].nir == NULL) {
2552 nir_shader *nir = nir_shader_clone(stage_ctx, stages[i].nir);
2555 brw_nir_lower_raygen(nir);
2559 brw_nir_lower_any_hit(nir, devinfo);
2563 brw_nir_lower_closest_hit(nir);
2567 brw_nir_lower_miss(nir);
2574 brw_nir_lower_callable(nir);
2581 result = compile_upload_rt_shader(pipeline, cache, nir, &stages[i],
2628 any_hit = stages[any_hit_idx].nir;
2632 nir_shader_clone(group_ctx, stages[intersection_idx].nir);
2723 .nir = trampoline_nir,
2775 .nir = trivial_return_nir,
3195 if (exe->nir) {
3201 if (!write_ir_text(ir, exe->nir))