Lines Matching defs:payload
280 uint32_t submission_id, const void* payload = nullptr,
325 if (payload && payload_as_extra) {
326 payload_as_extra(event, payload);
335 const struct trace_intel_end_stall *payload)
344 (payload->flags & INTEL_DS_DEPTH_CACHE_FLUSH_BIT) ? "+depth_flush" : "",
345 (payload->flags & INTEL_DS_DATA_CACHE_FLUSH_BIT) ? "+dc_flush" : "",
346 (payload->flags & INTEL_DS_HDC_PIPELINE_FLUSH_BIT) ? "+hdc_flush" : "",
347 (payload->flags & INTEL_DS_RENDER_TARGET_CACHE_FLUSH_BIT) ? "+rt_flush" : "",
348 (payload->flags & INTEL_DS_TILE_CACHE_FLUSH_BIT) ? "+tile_flush" : "",
349 (payload->flags & INTEL_DS_STATE_CACHE_INVALIDATE_BIT) ? "+state_inv" : "",
350 (payload->flags & INTEL_DS_CONST_CACHE_INVALIDATE_BIT) ? "+const_inv" : "",
351 (payload->flags & INTEL_DS_VF_CACHE_INVALIDATE_BIT) ? "+vf_inv" : "",
352 (payload->flags & INTEL_DS_TEXTURE_CACHE_INVALIDATE_BIT) ? "+tex_inv" : "",
353 (payload->flags & INTEL_DS_INST_CACHE_INVALIDATE_BIT) ? "+inst_inv" : "",
354 (payload->flags & INTEL_DS_STALL_AT_SCOREBOARD_BIT) ? "+pb_stall" : "",
355 (payload->flags & INTEL_DS_DEPTH_STALL_BIT) ? "+depth_stall" : "",
356 (payload->flags & INTEL_DS_HDC_PIPELINE_FLUSH_BIT) ? "+hdc_flush" : "",
357 (payload->flags & INTEL_DS_CS_STALL_BIT) ? "+cs_stall" : "",
358 payload->reason ? payload->reason : "unknown");
384 const struct trace_intel_begin_##event_name *payload) \
395 const struct trace_intel_end_##event_name *payload) \
400 payload, \
426 const struct trace_intel_begin_stall *payload)
437 const struct trace_intel_end_stall *payload)
442 payload,