Lines Matching defs:devinfo
52 print_regions_info(const struct intel_device_info *devinfo)
54 if (devinfo->mem.sram.mappable.size > 0 ||
55 devinfo->mem.sram.unmappable.size > 0) {
57 if (devinfo->mem.use_class_instance) {
59 devinfo->mem.sram.mem_class, devinfo->mem.sram.mem_instance);
62 devinfo->mem.sram.mappable.size);
64 devinfo->mem.sram.mappable.free);
65 if (devinfo->mem.sram.unmappable.size > 0) {
67 devinfo->mem.sram.unmappable.size);
69 devinfo->mem.sram.unmappable.free);
73 if (devinfo->mem.vram.mappable.size > 0 ||
74 devinfo->mem.vram.unmappable.size > 0) {
76 if (devinfo->mem.use_class_instance) {
78 devinfo->mem.vram.mem_class, devinfo->mem.vram.mem_instance);
81 devinfo->mem.vram.mappable.size);
83 devinfo->mem.vram.mappable.free);
84 if (devinfo->mem.vram.unmappable.size > 0) {
86 devinfo->mem.vram.unmappable.size);
88 devinfo->mem.vram.unmappable.free);
105 struct intel_device_info devinfo;
116 bool success = intel_get_device_info_from_fd(fd, &devinfo);
122 fprintf(stdout, "devinfo struct size = %zu\n", sizeof(devinfo));
126 fprintf(stdout, " name: %s\n", devinfo.name);
127 fprintf(stdout, " gen: %u\n", devinfo.ver);
128 fprintf(stdout, " PCI device id: 0x%x\n", devinfo.pci_device_id);
129 fprintf(stdout, " PCI domain: 0x%x\n", devinfo.pci_domain);
130 fprintf(stdout, " PCI bus: 0x%x\n", devinfo.pci_bus);
131 fprintf(stdout, " PCI dev: 0x%x\n", devinfo.pci_dev);
132 fprintf(stdout, " PCI function: 0x%x\n", devinfo.pci_func);
133 fprintf(stdout, " PCI revision id: 0x%x\n", devinfo.pci_revision_id);
134 fprintf(stdout, " revision: %u\n", devinfo.revision);
136 const char *subslice_name = devinfo.ver >= 12 ? "dualsubslice" : "subslice";
138 for (unsigned s = 0; s < devinfo.max_slices; s++) {
139 n_s += (devinfo.slice_masks & (1u << s)) ? 1 : 0;
140 for (unsigned ss = 0; ss < devinfo.max_subslices_per_slice; ss++) {
142 if (intel_device_info_subslice_available(&devinfo, s, ss)) {
144 for (unsigned eu = 0; eu < devinfo.max_eus_per_subslice; eu++) {
145 n_eus += intel_device_info_eu_available(&devinfo, s, ss, eu) ? 1 : 0;
146 fprintf(stdout, "%s", intel_device_info_eu_available(&devinfo, s, ss, eu) ? "1" : "0");
154 for (uint32_t pp = 0; pp < ARRAY_SIZE(devinfo.ppipe_subslices); pp++) {
156 pp, devinfo.ppipe_subslices[pp]);
162 fprintf(stdout, " EU threads: %u\n", n_eus * devinfo.num_thread_per_eu);
164 fprintf(stdout, " LLC: %u\n", devinfo.has_llc);
165 fprintf(stdout, " threads per EU: %u\n", devinfo.num_thread_per_eu);
166 fprintf(stdout, " URB size: %u\n", devinfo.urb.size);
167 fprintf(stdout, " L3 banks: %u\n", devinfo.l3_banks);
168 fprintf(stdout, " max VS threads: %u\n", devinfo.max_vs_threads);
169 fprintf(stdout, " max TCS threads: %u\n", devinfo.max_tcs_threads);
170 fprintf(stdout, " max TES threads: %u\n", devinfo.max_tes_threads);
171 fprintf(stdout, " max GS threads: %u\n", devinfo.max_gs_threads);
172 fprintf(stdout, " max WM threads: %u\n", devinfo.max_wm_threads);
173 fprintf(stdout, " max CS threads: %u\n", devinfo.max_cs_threads);
175 devinfo.timestamp_frequency, 1000000000.0 / devinfo.timestamp_frequency);
177 print_regions_info(&devinfo);