Lines Matching refs:emit
78 emit(TCS_OPCODE_GET_INSTANCE_ID, dst_reg(invocation_id));
86 emit(CMP(dst_null_d(), invocation_id,
91 emit(IF(BRW_PREDICATE_NORMAL));
103 emit(BRW_OPCODE_ENDIF);
117 emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
118 emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
128 emit(TCS_OPCODE_SRC0_010_IS_ZERO, dst_null_d(),
130 emit(IF(BRW_PREDICATE_NORMAL));
139 emit(TCS_OPCODE_RELEASE_INPUT, header, brw_imm_ud(i),
142 emit(BRW_OPCODE_ENDIF);
145 inst = emit(TCS_OPCODE_THREAD_END);
164 inst = emit(VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index,
169 inst = emit(VEC4_OPCODE_URB_READ, temp, src_reg(header));
179 emit(MOV(dst, swizzle(src_reg(temp), BRW_SWIZZLE_WWWW)));
183 emit(MOV(dst, src));
197 inst = emit(VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, header,
201 vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header));
209 emit(MOV(dst, swizzle(src_reg(read->dst),
226 inst = emit(VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, dst_reg(message),
229 inst = emit(MOV(byte_offset(dst_reg(retype(message, value.type)), REG_SIZE),
233 inst = emit(VEC4_TCS_OPCODE_URB_WRITE, dst_null_f(), message);
244 emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD),
248 emit(TCS_OPCODE_GET_PRIMITIVE_ID,
252 emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D),
309 emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
310 emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));