Lines Matching defs:nir
41 const nir_shader *nir,
45 nir, mem_ctx, false, debug_enabled),
85 if (nir->info.tess.tcs_vertices_out % 2) {
87 brw_imm_ud(nir->info.tess.tcs_vertices_out),
102 if (nir->info.tess.tcs_vertices_out % 2) {
359 nir_shader *nir = params->nir;
369 prog_data->base.base.ray_queries = nir->info.ray_queries;
372 nir->info.outputs_written = key->outputs_written;
373 nir->info.patch_outputs_written = key->patch_outputs_written;
376 brw_compute_vue_map(devinfo, &input_vue_map, nir->info.inputs_read,
377 nir->info.separate_shader, 1);
379 nir->info.outputs_written,
380 nir->info.patch_outputs_written);
382 brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
383 brw_nir_lower_vue_inputs(nir, &input_vue_map);
384 brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map,
387 brw_nir_apply_tcs_quads_workaround(nir);
389 brw_postprocess_nir(nir, compiler, is_scalar, debug_enabled,
393 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);
398 nir->info.tess.tcs_vertices_out <= (devinfo->ver >= 12 ? 32 : 16) &&
407 prog_data->instances = nir->info.tess.tcs_vertices_out;
413 DIV_ROUND_UP(nir->info.tess.tcs_vertices_out, verts_per_thread);
433 output_size_bytes += nir->info.tess.tcs_vertices_out *
458 &prog_data->base.base, nir, 8, debug_enabled);
471 nir->info.label ? nir->info.label
473 nir->info.name));
479 g.add_const_data(nir->constant_data, nir->constant_data_size);
484 nir, mem_ctx, debug_enabled);
494 assembly = brw_vec4_generate_assembly(compiler, params->log_data, mem_ctx, nir,