Lines Matching refs:dst
195 dst_reg dst =
198 dst.type = BRW_REGISTER_TYPE_DF;
199 nir_ssa_values[dest.ssa.index] = dst;
200 return dst;
293 const dst_reg dst = bld.vgrf(BRW_REGISTER_TYPE_DF);
294 ubld.DIM(dst, brw_imm_df(v));
295 return swizzle(src_reg(dst), BRW_SWIZZLE_XXXX);
495 * appropriate writemask in the dst register of the SEND instruction.
501 * on the dst of the SEND instruction to select the channels we want to
829 const dst_reg &dst,
862 bld.LZD(retype(dst, BRW_REGISTER_TYPE_UD),
870 inst = bld.ADD(dst, retype(src_reg(dst), BRW_REGISTER_TYPE_D),
876 vec4_visitor::emit_conversion_from_double(dst_reg dst, src_reg src)
879 switch (dst.type) {
898 emit(VEC4_OPCODE_PICK_LOW_32BIT, retype(temp2, dst.type), src_reg(temp2));
899 emit(MOV(dst, src_reg(retype(temp2, dst.type))));
903 vec4_visitor::emit_conversion_to_double(dst_reg dst, src_reg src)
909 emit(MOV(dst, src_reg(tmp_dst)));
1118 dst_reg dst = get_nir_dest(instr->dest.dest, dst_type);
1119 dst.writemask = instr->dest.write_mask;
1147 inst = emit(MOV(dst, op[0]));
1157 inst = emit(MOV(dst, op[0]));
1164 emit_conversion_from_double(dst, op[0]);
1166 inst = emit(MOV(dst, op[0]));
1172 emit_conversion_to_double(dst, op[0]);
1176 inst = emit(MOV(dst, op[0]));
1183 inst = emit(MOV(dst, op[0]));
1190 inst = emit(MOV(dst, op[0]));
1198 inst = emit(ADD(dst, op[0], op[1]));
1203 inst = emit(ADD(dst, op[0], op[1]));
1209 inst = emit(MUL(dst, op[0], op[1]));
1225 emit(MUL(dst, op[0], op[1]));
1227 emit(MUL(dst, op[1], op[0]));
1232 emit(MUL(dst, op[1], op[0]));
1234 emit(MUL(dst, op[0], op[1]));
1236 struct brw_reg acc = retype(brw_acc_reg(8), dst.type);
1240 emit(MOV(dst, src_reg(acc)));
1248 struct brw_reg acc = retype(brw_acc_reg(8), dst.type);
1251 emit(MACH(dst, op[0], op[1]));
1256 inst = emit_math(SHADER_OPCODE_RCP, dst, op[0]);
1260 inst = emit_math(SHADER_OPCODE_EXP2, dst, op[0]);
1264 inst = emit_math(SHADER_OPCODE_LOG2, dst, op[0]);
1268 inst = emit_math(SHADER_OPCODE_SIN, dst, op[0]);
1272 inst = emit_math(SHADER_OPCODE_COS, dst, op[0]);
1278 emit_math(SHADER_OPCODE_INT_QUOTIENT, dst, op[0], op[1]);
1288 emit_math(SHADER_OPCODE_INT_REMAINDER, dst, op[0], op[1]);
1293 inst = emit_math(SHADER_OPCODE_INT_REMAINDER, dst, op[0], op[1]);
1296 inst = emit(MOV(dst_null_d(), src_reg(dst)));
1317 inst = emit(ADD(dst, src_reg(dst), op[1]));
1326 inst = emit_math(SHADER_OPCODE_SQRT, dst, op[0]);
1330 inst = emit_math(SHADER_OPCODE_RSQ, dst, op[0]);
1334 inst = emit_math(SHADER_OPCODE_POW, dst, op[0], op[1]);
1342 emit(MOV(dst, src_reg(acc)));
1351 emit(MOV(dst, src_reg(acc)));
1356 inst = emit(RNDZ(dst, op[0]));
1359 inst = emit(ADD(dst, src_reg(dst), brw_imm_f(1.0f)));
1361 inst = emit(MOV(dst, src_reg(dst))); /* for potential saturation */
1375 inst = emit(MOV(dst, tmp));
1380 inst = emit(RNDD(dst, op[0]));
1384 inst = emit(FRC(dst, op[0]));
1388 inst = emit(RNDE(dst, op[0]));
1391 inst = emit(ADD(dst, src_reg(dst), brw_imm_f(1.0f)));
1393 inst = emit(MOV(dst, src_reg(dst))); /* for potential saturation */
1416 inst = emit(BRW_OPCODE_SEL, dst, zero, tmp32);
1427 inst = emit_minmax(BRW_CONDITIONAL_L, dst, op[0], op[1]);
1436 inst = emit_minmax(BRW_CONDITIONAL_GE, dst, op[0], op[1]);
1469 emit(CMP(dst, op[0], op[1], conditional_mod));
1480 emit(MOV(dst, src_reg(result)));
1498 emit(MOV(dst, brw_imm_d(0)));
1499 inst = emit(MOV(dst, brw_imm_d(~0)));
1518 emit(MOV(dst, brw_imm_d(0)));
1519 inst = emit(MOV(dst, brw_imm_d(~0)));
1526 emit(NOT(dst, op[0]));
1532 emit(XOR(dst, op[0], op[1]));
1538 emit(OR(dst, op[0], op[1]));
1544 emit(AND(dst, op[0], op[1]));
1551 assert(dst.type == BRW_REGISTER_TYPE_DF);
1552 emit_conversion_to_double(dst, negate(op[0]));
1554 emit(MOV(dst, negate(op[0])));
1572 inst = emit(BRW_OPCODE_SEL, dst, one, brw_imm_d(0));
1575 emit(CMP(dst, op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ));
1580 emit(CMP(dst, op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ));
1608 emit(OR(dst, src_reg(tmp1), src_reg(tmp2)));
1619 emit(MOV(dst, src_reg(result)));
1631 emit(MOV(dst, src_reg(tmp2)));
1645 emit_unpack_half_2x16(dst, op[0]);
1649 emit_pack_half_2x16(dst, op[0]);
1654 emit_unpack_unorm_4x8(dst, op[0]);
1659 emit_pack_unorm_4x8(dst, op[0]);
1664 emit_unpack_snorm_4x8(dst, op[0]);
1669 emit_pack_snorm_4x8(dst, op[0]);
1674 emit(BFREV(dst, op[0]));
1679 emit(CBIT(dst, op[0]));
1684 emit_find_msb_using_lzd(vec4_builder(this).at_end(), dst, op[0], false);
1690 src_reg src(dst);
1693 emit_find_msb_using_lzd(bld, dst, op[0], true);
1695 emit(FBH(retype(dst, BRW_REGISTER_TYPE_UD), op[0]));
1704 inst = bld.ADD(dst, src, brw_imm_d(31));
1731 emit_find_msb_using_lzd(bld, dst, src_reg(temp), false);
1733 bld.FBL(dst, op[0]);
1748 emit(BFE(dst, op[2], op[1], op[0]));
1753 emit(BFI1(dst, op[0], op[1]));
1762 emit(BFI2(dst, op[0], op[1], op[2]));
1778 dst.type = BRW_REGISTER_TYPE_UD;
1779 emit(AND(dst, op[0], brw_imm_ud(0x80000000u)));
1781 inst = emit(OR(dst, src_reg(dst), brw_imm_ud(0x3f800000u)));
1783 dst.type = BRW_REGISTER_TYPE_F;
1814 emit_conversion_to_double(dst, retype(src_reg(tmp),
1822 emit(SHL(dst, op[0], op[1]));
1828 emit(ASR(dst, op[0], op[1]));
1834 emit(SHR(dst, op[0], op[1]));
1838 if (type_sz(dst.type) == 8) {
1841 inst = emit(ADD(dst, src_reg(mul_dst), op[2]));
1844 inst = emit(MAD(dst, op[2], op[1], op[0]));
1850 inst = emit(LRP(dst, op[2], op[1], op[0]));
1857 switch (dst.writemask) {
1875 inst = emit(BRW_OPCODE_SEL, dst, op[1], op[2]);
1881 inst = emit(BRW_OPCODE_DP2, dst, op[0], op[1]);
1886 inst = emit(BRW_OPCODE_DP3, dst, op[0], op[1]);
1891 inst = emit(BRW_OPCODE_DP4, dst, op[0], op[1]);
1896 inst = emit(BRW_OPCODE_DPH, dst, op[0], op[1]);
1920 masked.writemask = dst.writemask;
1921 emit(AND(masked, src_reg(dst), brw_imm_d(1)));
1924 emit(MOV(retype(dst, BRW_REGISTER_TYPE_D), masked_neg));
2143 inst->dst.writemask = WRITEMASK_XYZW;
2157 inst->dst.writemask = WRITEMASK_X;
2277 emit_minmax(BRW_CONDITIONAL_GE, writemask(inst->dst, WRITEMASK_Z),
2278 src_reg(inst->dst), brw_imm_d(1));
2315 return src_reg(inst->dst);
2353 * Notice that @src and @dst cannot be the same register.
2356 vec4_visitor::shuffle_64bit_data(dst_reg dst, src_reg src, bool for_write,
2361 assert(type_sz(dst.type) == 8);
2362 assert(!regions_overlap(dst, 2 * REG_SIZE, src, 2 * REG_SIZE));
2377 /* dst+0.XY = src+0.XY */
2378 bld.group(4, 0).emit(mov_op, writemask(dst, WRITEMASK_XY), src);
2380 /* dst+0.ZW = src+1.XY */
2382 .emit(mov_op, writemask(dst, WRITEMASK_ZW),
2385 /* dst+1.XY = src+0.ZW */
2387 .emit(mov_op, writemask(byte_offset(dst, REG_SIZE), WRITEMASK_XY),
2390 /* dst+1.ZW = src+1.ZW */
2392 .emit(mov_op, writemask(byte_offset(dst, REG_SIZE), WRITEMASK_ZW),