Lines Matching defs:instr
132 nir_foreach_instr(instr, block) {
133 nir_emit_instr(instr);
138 vec4_visitor::nir_emit_instr(nir_instr *instr)
140 base_ir = instr;
142 switch (instr->type) {
144 nir_emit_load_const(nir_instr_as_load_const(instr));
148 nir_emit_intrinsic(nir_instr_as_intrinsic(instr));
152 nir_emit_alu(nir_instr_as_alu(instr));
156 nir_emit_jump(nir_instr_as_jump(instr));
160 nir_emit_texture(nir_instr_as_tex(instr));
164 nir_emit_undef(nir_instr_as_ssa_undef(instr));
266 vec4_visitor::get_indirect_offset(nir_intrinsic_instr *instr)
268 nir_src *offset_src = nir_get_io_offset_src(instr);
273 * into instr->const_index[0].
327 vec4_visitor::nir_emit_load_const(nir_load_const_instr *instr)
331 if (instr->def.bit_size == 64) {
340 unsigned remaining = brw_writemask_for_size(instr->def.num_components);
346 for (unsigned i = 0; i < instr->def.num_components; i++) {
352 for (unsigned j = i; j < instr->def.num_components; j++) {
353 if ((instr->def.bit_size == 32 &&
354 instr->value[i].u32 == instr->value[j].u32) ||
355 (instr->def.bit_size == 64 &&
356 instr->value[i].f64 == instr->value[j].f64)) {
362 if (instr->def.bit_size == 64) {
363 emit(MOV(reg, setup_imm_df(ibld, instr->value[i].f64)));
365 emit(MOV(reg, brw_imm_d(instr->value[i].i32)));
372 reg.writemask = brw_writemask_for_size(instr->def.num_components);
374 nir_ssa_values[instr->def.index] = reg;
378 vec4_visitor::get_nir_ssbo_intrinsic_index(nir_intrinsic_instr *instr)
381 const unsigned src = instr->intrinsic == nir_intrinsic_store_ssbo ? 1 : 0;
383 if (nir_src_is_const(instr->src[src])) {
384 return brw_imm_ud(nir_src_as_uint(instr->src[src]));
386 return emit_uniformize(get_nir_src(instr->src[src]));
391 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
396 switch (instr->intrinsic) {
399 assert(nir_dest_bit_size(instr->dest) == 32);
401 unsigned load_offset = nir_src_as_uint(instr->src[0]);
403 dest = get_nir_dest(instr->dest);
404 dest.writemask = brw_writemask_for_size(instr->num_components);
406 src = src_reg(ATTR, instr->const_index[0] + load_offset,
411 src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr));
417 assert(nir_src_bit_size(instr->src[0]) == 32);
418 unsigned store_offset = nir_src_as_uint(instr->src[1]);
419 int varying = instr->const_index[0] + store_offset;
420 src = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_F,
421 instr->num_components);
423 unsigned c = nir_intrinsic_component(instr);
425 output_num_components[varying][c] = instr->num_components;
430 assert(nir_src_num_components(instr->src[0]) == 1);
431 unsigned ssbo_index = nir_src_is_const(instr->src[0]) ?
432 nir_src_as_uint(instr->src[0]) : 0;
434 dst_reg result_dst = get_nir_dest(instr->dest);
456 assert(nir_src_bit_size(instr->src[0]) == 32);
457 assert(nir_intrinsic_write_mask(instr) ==
458 (1u << instr->num_components) - 1);
460 src_reg surf_index = get_nir_ssbo_intrinsic_index(instr);
461 src_reg offset_reg = retype(get_nir_src_imm(instr->src[2]),
465 src_reg val_reg = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_F, 4);
509 1 /* dims */, instr->num_components /* size */,
518 assert(nir_dest_bit_size(instr->dest) == 32);
520 src_reg surf_index = get_nir_ssbo_intrinsic_index(instr);
521 src_reg offset_reg = retype(get_nir_src_imm(instr->src[1]),
531 dst_reg dest = get_nir_dest(instr->dest);
533 read_result.swizzle = brw_swizzle_for_size(instr->num_components);
548 nir_emit_ssbo_atomic(brw_aop_for_nir_intrinsic(instr), instr);
564 assert(nir_intrinsic_base(instr) % 4 == 0);
566 dest = get_nir_dest(instr->dest);
568 src = src_reg(dst_reg(UNIFORM, nir_intrinsic_base(instr) / 16));
580 unsigned shift = (nir_intrinsic_base(instr) % 16) / type_size;
581 assert(shift + instr->num_components <= 4);
583 if (nir_src_is_const(instr->src[0])) {
584 const unsigned load_offset = nir_src_as_uint(instr->src[0]);
588 src.swizzle = brw_swizzle_for_size(instr->num_components);
589 dest.writemask = brw_writemask_for_size(instr->num_components);
593 assert(shift + instr->num_components <= 4);
603 src_reg indirect = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_UD, 1);
609 indirect, brw_imm_ud(instr->const_index[1]));
617 dest = get_nir_dest(instr->dest);
619 if (nir_src_is_const(instr->src[0])) {
623 const unsigned index = nir_src_as_uint(instr->src[0]);
631 emit(MOV(dst_reg(surf_index), get_nir_src(instr->src[0], nir_type_int32,
632 instr->num_components)));
638 if (nir_src_is_const(instr->src[1])) {
639 unsigned load_offset = nir_src_as_uint(instr->src[1]);
644 if (nir_src_is_const(instr->src[0])) {
645 const unsigned ubo_block = nir_src_as_uint(instr->src[0]);
664 get_nir_src(instr->src[1], nir_type_uint32, 1)));
670 } else if (nir_dest_bit_size(instr->dest) == 32) {
695 packed_consts.swizzle = brw_swizzle_for_size(instr->num_components);
696 if (nir_src_is_const(instr->src[1])) {
697 unsigned load_offset = nir_src_as_uint(instr->src[1]);
712 assert(nir_intrinsic_execution_scope(instr) == NIR_SCOPE_NONE);
729 dest = get_nir_dest(instr->dest, type);
740 vec4_visitor::nir_emit_ssbo_atomic(int op, nir_intrinsic_instr *instr)
743 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
744 dest = get_nir_dest(instr->dest);
746 src_reg surface = get_nir_ssbo_intrinsic_index(instr);
747 src_reg offset = get_nir_src(instr->src[1], 1);
750 data1 = get_nir_src(instr->src[2], 1);
753 data2 = get_nir_src(instr->src[3], 1);
775 vec4_visitor::optimize_predicate(nir_alu_instr *instr,
778 if (!instr->src[0].src.is_ssa ||
779 instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
783 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
932 try_immediate_source(const nir_alu_instr *instr, src_reg *op,
941 assert(nir_op_infos[instr->op].num_inputs > 1 ||
942 instr->op == nir_op_mov);
944 if (instr->op != nir_op_mov &&
945 nir_src_bit_size(instr->src[1].src) == 32 &&
946 nir_src_is_const(instr->src[1].src)) {
949 nir_src_bit_size(instr->src[0].src) == 32 &&
950 nir_src_is_const(instr->src[0].src)) {
965 if (nir_alu_instr_channel_used(instr, idx, i)) {
968 d = nir_src_comp_as_int(instr->src[idx].src,
969 instr->src[idx].swizzle[i]);
970 } else if (d != nir_src_comp_as_int(instr->src[idx].src,
971 instr->src[idx].swizzle[i])) {
995 if (nir_alu_instr_channel_used(instr, idx, i)) {
996 f[i] = nir_src_comp_as_float(instr->src[idx].src,
997 instr->src[idx].swizzle[i]);
1047 if (idx == 0 && instr->op != nir_op_mov) {
1057 vec4_visitor::fix_float_operands(src_reg op[3], nir_alu_instr *instr)
1062 if (!nir_src_is_const(instr->src[i].src))
1069 if (!nir_src_is_const(instr->src[j].src))
1072 if (nir_alu_srcs_equal(instr, instr, i, j)) {
1080 } else if (nir_alu_srcs_negative_equal(instr, instr, i, j)) {
1112 vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
1116 nir_alu_type dst_type = (nir_alu_type) (nir_op_infos[instr->op].output_type |
1117 nir_dest_bit_size(instr->dest.dest));
1118 dst_reg dst = get_nir_dest(instr->dest.dest, dst_type);
1119 dst.writemask = instr->dest.write_mask;
1121 assert(!instr->dest.saturate);
1124 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
1126 assert(!instr->src[i].abs);
1127 assert(!instr->src[i].negate);
1130 (nir_op_infos[instr->op].input_types[i] |
1131 nir_src_bit_size(instr->src[i].src));
1132 op[i] = get_nir_src(instr->src[i].src, src_type, 4);
1133 op[i].swizzle = brw_swizzle_for_nir_swizzle(instr->src[i].swizzle);
1140 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1144 switch (instr->op) {
1146 try_immediate_source(instr, &op[0], true);
1163 if (nir_src_bit_size(instr->src[0].src) == 64)
1194 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1197 try_immediate_source(instr, op, true);
1202 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1208 try_immediate_source(instr, op, true);
1213 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1221 if (nir_src_is_const(instr->src[0].src) &&
1222 nir_alu_instr_src_read_mask(instr, 0) == 1 &&
1223 const_src_fits_in_16_bits(instr->src[0].src, op[0].type)) {
1228 } else if (nir_src_is_const(instr->src[1].src) &&
1229 nir_alu_instr_src_read_mask(instr, 1) == 1 &&
1230 const_src_fits_in_16_bits(instr->src[1].src, op[1].type)) {
1247 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1277 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1287 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1338 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1347 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1368 brw_swizzle_for_size(instr->src[0].src.is_ssa ?
1369 instr->src[0].src.ssa->num_components :
1370 instr->src[0].src.reg.reg->num_components);
1423 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1426 try_immediate_source(instr, op, true);
1432 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1435 try_immediate_source(instr, op, true);
1453 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1460 brw_cmod_for_nir_comparison(instr->op);
1462 if (nir_src_bit_size(instr->src[0].src) < 64) {
1466 if (try_immediate_source(instr, op, true) == 0)
1488 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1494 brw_swizzle_for_size(nir_op_infos[instr->op].input_sizes[0]);
1497 brw_cmod_for_nir_comparison(instr->op)));
1507 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1513 brw_swizzle_for_size(nir_op_infos[instr->op].input_sizes[0]);
1516 brw_cmod_for_nir_comparison(instr->op)));
1525 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1530 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1531 try_immediate_source(instr, op, true);
1536 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1537 try_immediate_source(instr, op, true);
1542 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1543 try_immediate_source(instr, op, true);
1550 if (nir_dest_bit_size(instr->dest.dest) > 32) {
1559 if (nir_src_bit_size(instr->src[0].src) == 64) {
1625 enum opcode oper = (instr->op == nir_op_unpack_64_2x32_split_x) ?
1653 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1658 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1663 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1668 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1673 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1678 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1683 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1688 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1712 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1743 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1752 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1757 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1820 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1821 try_immediate_source(instr, op, false);
1826 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1827 try_immediate_source(instr, op, false);
1832 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1833 try_immediate_source(instr, op, false);
1843 fix_float_operands(op, instr);
1849 fix_float_operands(op, instr);
1855 if (!optimize_predicate(instr, &predicate)) {
1880 try_immediate_source(instr, op, true);
1885 try_immediate_source(instr, op, true);
1890 try_immediate_source(instr, op, true);
1895 try_immediate_source(instr, op, false);
1917 (instr->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) ==
1929 vec4_visitor::nir_emit_jump(nir_jump_instr *instr)
1931 switch (instr->type) {
1957 vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
1959 unsigned texture = instr->texture_index;
1960 unsigned sampler = instr->sampler_index;
1971 dst_reg dest = get_nir_dest(instr->dest, instr->dest_type);
1974 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
1979 for (unsigned i = 0; i < instr->num_srcs; i++) {
1980 switch (instr->src[i].src_type) {
1982 shadow_comparator = get_nir_src(instr->src[i].src,
1987 unsigned src_size = nir_tex_instr_src_size(instr, i);
1989 switch (instr->op) {
1993 coordinate = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D,
1999 coordinate = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_F,
2008 lod = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_F,
2009 nir_tex_instr_src_size(instr, i));
2013 lod2 = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_F,
2014 nir_tex_instr_src_size(instr, i));
2018 switch (instr->op) {
2021 lod = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D, 1);
2025 lod = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_F, 1);
2031 sample_index = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D, 1);
2036 if (!brw_texture_offset(instr, i, &constant_offset)) {
2038 get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D, 2);
2044 src_reg src = get_nir_src(instr->src[i].src, 1);
2053 src_reg src = get_nir_src(instr->src[i].src, 1);
2071 if (instr->op == nir_texop_txf_ms ||
2072 instr->op == nir_texop_samples_identical) {
2083 if (instr->op == nir_texop_tg4) {
2084 if (instr->component == 1 &&
2091 constant_offset |= instr->component << 16;
2096 switch (instr->op) {
2161 int coord_mask = (1 << instr->coord_components) - 1;
2232 if (nir_tex_instr_dest_size(instr) == 3 ||
2275 if (instr->op == nir_texop_txs && devinfo->ver < 7) {
2281 if (instr->op == nir_texop_query_levels) {
2319 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr *instr)
2321 nir_ssa_values[instr->def.index] =
2322 dst_reg(VGRF, alloc.allocate(DIV_ROUND_UP(instr->def.bit_size, 32)));