Lines Matching defs:dest
192 vec4_visitor::get_nir_dest(const nir_dest &dest)
194 if (dest.is_ssa) {
196 dst_reg(VGRF, alloc.allocate(DIV_ROUND_UP(dest.ssa.bit_size, 32)));
197 if (dest.ssa.bit_size == 64)
199 nir_ssa_values[dest.ssa.index] = dst;
202 return dst_reg_for_nir_reg(this, dest.reg.reg, dest.reg.base_offset,
203 dest.reg.indirect);
208 vec4_visitor::get_nir_dest(const nir_dest &dest, enum brw_reg_type type)
210 return retype(get_nir_dest(dest), type);
214 vec4_visitor::get_nir_dest(const nir_dest &dest, nir_alu_type type)
216 return get_nir_dest(dest, brw_type_for_nir_type(devinfo, type));
393 dst_reg dest;
399 assert(nir_dest_bit_size(instr->dest) == 32);
403 dest = get_nir_dest(instr->dest);
404 dest.writemask = brw_writemask_for_size(instr->num_components);
408 src = retype(src, dest.type);
412 emit(MOV(dest, src));
434 dst_reg result_dst = get_nir_dest(instr->dest);
518 assert(nir_dest_bit_size(instr->dest) == 32);
531 dst_reg dest = get_nir_dest(instr->dest);
532 read_result.type = dest.type;
534 emit(MOV(dest, read_result));
566 dest = get_nir_dest(instr->dest);
569 src.type = dest.type;
589 dest.writemask = brw_writemask_for_size(instr->num_components);
596 emit(MOV(dest, src));
606 dest.writemask = WRITEMASK_XYZW;
608 emit(SHADER_OPCODE_MOV_INDIRECT, dest, src,
617 dest = get_nir_dest(instr->dest);
655 push_reg.type = dest.type;
670 } else if (nir_dest_bit_size(instr->dest) == 32) {
698 unsigned type_size = type_sz(dest.type);
706 emit(MOV(dest, retype(packed_consts, dest.type)));
729 dest = get_nir_dest(instr->dest, type);
730 emit(MOV(dest, shader_clock));
742 dst_reg dest;
744 dest = get_nir_dest(instr->dest);
764 dest.type = atomic_result.type;
765 bld.MOV(dest, atomic_result);
1117 nir_dest_bit_size(instr->dest.dest));
1118 dst_reg dst = get_nir_dest(instr->dest.dest, dst_type);
1119 dst.writemask = instr->dest.write_mask;
1121 assert(!instr->dest.saturate);
1194 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1202 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1213 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1247 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1277 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1287 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1338 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1347 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1423 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1432 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1453 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1488 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1507 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1525 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1530 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1536 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1542 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1550 if (nir_dest_bit_size(instr->dest.dest) > 32) {
1653 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1658 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1663 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1668 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1673 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1678 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1683 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1688 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1712 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1743 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1752 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1757 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1820 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1826 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1832 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1971 dst_reg dest = get_nir_dest(instr->dest, instr->dest_type);
2113 emit(MOV(dest, brw_imm_ud(0u)));
2123 vec4_instruction *inst = new(mem_ctx) vec4_instruction(opcode, dest);
2283 src_reg swizzled(dest);
2286 emit(MOV(dest, swizzled));