Lines Matching refs:inst
49 is_expression(const vec4_instruction *const inst)
51 switch (inst->opcode) {
91 return inst->mlen == 0;
174 foreach_inst_in_block (vec4_instruction, inst, block) {
176 if (is_expression(inst) && !inst->predicate && inst->mlen == 0 &&
177 ((inst->dst.file != ARF && inst->dst.file != FIXED_GRF) ||
178 inst->dst.is_null()))
184 if (!(entry->generator->dst.is_null() && !inst->dst.is_null()) &&
185 instructions_match(inst, entry->generator)) {
193 if (inst->opcode != BRW_OPCODE_MOV ||
194 (inst->opcode == BRW_OPCODE_MOV &&
195 inst->src[0].file == IMM &&
196 inst->src[0].type == BRW_REGISTER_TYPE_VF)) {
200 entry->generator = inst;
211 NULL), inst->dst.type);
232 if (!inst->dst.is_null()) {
233 assert(inst->dst.type == entry->tmp.type);
234 const unsigned width = inst->exec_size;
235 unsigned component_size = width * type_sz(inst->dst.type);
237 DIV_ROUND_UP(inst->size_written, component_size);
240 MOV(offset(inst->dst, width, i),
242 copy->exec_size = inst->exec_size;
243 copy->group = inst->group;
244 copy->force_writemask_all = inst->force_writemask_all;
245 inst->insert_before(block, copy);
249 /* Set our iterator so that next time through the loop inst->next
253 vec4_instruction *prev = (vec4_instruction *)inst->prev;
255 inst->remove(block);
256 inst = prev;
264 if (inst->writes_flag(devinfo)) {
267 !instructions_match(inst, entry->generator))) {
280 if (inst->dst.file == entry->generator->src[i].file &&
281 inst->dst.nr == entry->generator->src[i].nr) {