Lines Matching defs:const

49 src_reg::src_reg(enum brw_reg_file file, int nr, const glsl_type *type)
76 src_reg::src_reg(const dst_reg &reg) :
105 dst_reg::dst_reg(enum brw_reg_file file, int nr, const glsl_type *type,
134 dst_reg::dst_reg(const src_reg &reg) :
142 dst_reg::equals(const dst_reg &r) const
150 vec4_instruction::is_send_from_grf() const
187 vec4_instruction::has_source_and_destination_hazard() const
206 vec4_instruction::size_read(unsigned arg) const
237 vec4_instruction::can_do_source_mods(const struct intel_device_info *devinfo)
272 vec4_instruction::can_do_writemask(const struct intel_device_info *devinfo)
308 vec4_instruction::can_change_types() const
327 vec4_instruction::implied_mrf_writes() const
381 src_reg::equals(const src_reg &r) const
388 src_reg::negative_equals(const src_reg &r) const
565          const unsigned new_swizzle =
723 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction *inst)
847 vec4_instruction::can_reswizzle(const struct intel_device_info *devinfo,
917                const unsigned imm[] = {
954    const vec4_live_variables &live = live_analysis.require();
1004       const unsigned chans_needed =
1306 vec4_visitor::dump_instruction(const backend_instruction *be_inst) const
1312 vec4_visitor::dump_instruction(const backend_instruction *be_inst, FILE *file) const
1314    const vec4_instruction *inst = (const vec4_instruction *)be_inst;
1380       const unsigned reg_size = (inst->dst.file == UNIFORM ? 16 : REG_SIZE);
1473          const unsigned reg_size = (inst->src[i].file == UNIFORM ? 16 : REG_SIZE);
1479          static const char *chans[4] = {"x", "y", "z", "w"};
1539    const unsigned max_push_length = 32;
1562    ASSERTED const unsigned old_push_length = push_length;
1614       const vec4_builder ibld(this, block, inst);
1701          const unsigned size_written = type_sz(inst->dst.type);
1702          const unsigned num_regs = DIV_ROUND_UP(size_written, REG_SIZE);
1866 get_lowered_simd_width(const struct intel_device_info *devinfo,
1868                        unsigned stage, const vec4_instruction *inst)
1962       const unsigned lowered_width =
2109    const src_reg &src = inst->src[arg];
2359       const unsigned mask_param = stage_prog_data->push_reg_mask_param;
2475       const int grf_count = alloc.count;
2533 const unsigned *
2534 brw_compile_vs(const struct brw_compiler *compiler,
2539    const struct brw_vs_prog_key *key = params->key;
2541    const bool debug_enabled =
2548    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_VERTEX];
2551    const unsigned *assembly = NULL;
2620    const unsigned vue_entries =
2651          const char *debug_name =