Lines Matching defs:width
237 unsigned width:3; /* src only, align1 only */
389 * \param width one of BRW_WIDTH_x
402 unsigned width,
436 reg.width = width;
528 brw_vecn_reg(unsigned width, enum brw_reg_file file,
531 switch (width) {
543 unreachable("Invalid register width");
749 imm.width = BRW_WIDTH_4;
798 brw_vecn_grf(unsigned width, unsigned nr, unsigned subnr)
800 return brw_vecn_reg(width, BRW_GENERAL_REGISTER_FILE, nr, subnr);
825 brw_null_vec(unsigned width)
827 return brw_vecn_reg(width, BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_NULL, 0);
891 brw_acc_reg(unsigned width)
893 return brw_vecn_reg(width, BRW_ARCHITECTURE_REGISTER_FILE,
956 brw_uvec_mrf(unsigned width, unsigned nr, unsigned subnr)
958 return retype(brw_vecn_reg(width, BRW_MESSAGE_REGISTER_FILE, nr, subnr),
980 stride(struct brw_reg reg, unsigned vstride, unsigned width, unsigned hstride)
983 reg.width = cvt(width) - 1;
1233 reg.width == w &&
1251 } else if (reg.width == BRW_WIDTH_1 &&
1258 assert(reg.vstride == reg.hstride + reg.width);