Lines Matching defs:nir
28 #include "compiler/nir/nir_builder.h"
68 brw_nir_lower_load_uniforms(nir_shader *nir)
70 return nir_shader_lower_instructions(nir, brw_nir_lower_load_uniforms_filter,
94 brw_nir_lower_tue_outputs(nir_shader *nir, brw_tue_map *map)
105 nir_foreach_shader_out_variable(var, nir) {
110 NIR_PASS(_, nir, nir_lower_io, nir_var_shader_out,
123 nir->info.task_payload_size = map->per_task_data_start_dw * 4;
124 NIR_PASS(_, nir, nir_lower_vars_to_explicit_types,
126 NIR_PASS(_, nir, nir_lower_explicit_io,
129 map->size_dw = ALIGN(DIV_ROUND_UP(nir->info.task_payload_size, 4), 8);
175 brw_nir_adjust_task_payload_offsets(nir_shader *nir)
177 return nir_shader_instructions_pass(nir,
201 struct nir_shader *nir = params->nir;
207 prog_data->base.base.total_shared = nir->info.shared_size;
210 prog_data->base.local_size[0] = nir->info.workgroup_size[0];
211 prog_data->base.local_size[1] = nir->info.workgroup_size[1];
212 prog_data->base.local_size[2] = nir->info.workgroup_size[2];
215 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID);
217 brw_nir_lower_tue_outputs(nir, &prog_data->map);
220 brw_required_dispatch_width(&nir->info);
232 nir_shader *shader = nir_shader_clone(mem_ctx, nir);
280 nir->info.label ? nir->info.label
282 nir->info.name));
296 brw_nir_lower_tue_inputs(nir_shader *nir, const brw_tue_map *map)
301 nir->info.task_payload_size = map->per_task_data_start_dw * 4;
305 NIR_PASS(progress, nir, nir_lower_vars_to_explicit_types,
312 assert(map->size_dw == ALIGN(DIV_ROUND_UP(nir->info.task_payload_size, 4), 8));
318 nir->info.task_payload_size = 0;
321 NIR_PASS(_, nir, nir_lower_explicit_io, nir_var_mem_task_payload,
349 brw_compute_mue_map(struct nir_shader *nir, struct brw_mue_map *map)
357 num_mesh_vertices_per_primitive(nir->info.mesh.primitive_type);
359 map->max_primitives = nir->info.mesh.max_primitives_out;
360 map->max_vertices = nir->info.mesh.max_vertices_out;
362 uint64_t outputs_written = nir->info.outputs_written;
381 (nir->info.outputs_written & (BITFIELD64_BIT(VARYING_SLOT_VIEWPORT) |
389 u_foreach_bit64(location, outputs_written & nir->info.per_primitive_outputs) {
428 nir->info.clip_distance_array_size +
429 nir->info.cull_distance_array_size, 8);
431 u_foreach_bit64(location, outputs_written & ~nir->info.per_primitive_outputs) {
522 brw_nir_lower_mue_outputs(nir_shader *nir, const struct brw_mue_map *map)
524 nir_foreach_shader_out_variable(var, nir) {
531 NIR_PASS(_, nir, nir_lower_io, nir_var_shader_out,
536 brw_nir_initialize_mue(nir_shader *nir,
543 nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
552 assert(!nir->info.workgroup_size_variable);
553 const unsigned workgroup_size = nir->info.workgroup_size[0] *
554 nir->info.workgroup_size[1] *
555 nir->info.workgroup_size[2];
676 brw_nir_adjust_offset_for_arrayed_indices(nir_shader *nir, const struct brw_mue_map *map)
678 return nir_shader_instructions_pass(nir,
690 struct nir_shader *nir = params->nir;
696 prog_data->base.base.total_shared = nir->info.shared_size;
699 prog_data->base.local_size[0] = nir->info.workgroup_size[0];
700 prog_data->base.local_size[1] = nir->info.workgroup_size[1];
701 prog_data->base.local_size[2] = nir->info.workgroup_size[2];
703 prog_data->clip_distance_mask = (1 << nir->info.clip_distance_array_size) - 1;
705 ((1 << nir->info.cull_distance_array_size) - 1) <<
706 nir->info.clip_distance_array_size;
707 prog_data->primitive_type = nir->info.mesh.primitive_type;
713 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID);
715 brw_nir_lower_tue_inputs(nir, params->tue_map);
717 brw_compute_mue_map(nir, &prog_data->map);
718 brw_nir_lower_mue_outputs(nir, &prog_data->map);
721 brw_required_dispatch_width(&nir->info);
733 nir_shader *shader = nir_shader_clone(mem_ctx, nir);
797 nir->info.label ? nir->info.label
799 nir->info.name));