Lines Matching refs:file
40 fs_reg(enum brw_reg_file file, int nr);
41 fs_reg(enum brw_reg_file file, int nr, enum brw_reg_type type);
60 assert(reg.file != IMM);
75 switch (reg.file) {
106 switch (reg.file) {
128 unreachable("Invalid register file");
134 switch (reg.file) {
167 * its own, only the VGRF file is composed of multiple discrete address
173 return r.file << 16 | (r.file == VGRF ? r.nr : 0);
183 return (r.file == VGRF || r.file == IMM ? 0 : r.nr) *
184 (r.file == UNIFORM ? 4 : REG_SIZE) + r.offset +
185 (r.file == ARF || r.file == FIXED_GRF ? r.subnr : 0);
191 * one, or zero if components are tightly packed in the register file.
196 const unsigned stride = ((r.file != ARF && r.file != FIXED_GRF) ? r.stride :
210 if (r.file == MRF && (r.nr & BRW_MRF_COMPR4)) {
219 } else if (s.file == MRF && (s.nr & BRW_MRF_COMPR4)) {
250 if (reg.file == BAD_FILE || reg.is_null()) {
253 } else if (reg.file == IMM) {
260 } else if (reg.file == ARF || reg.file == FIXED_GRF) {
296 if (reg.file == ARF || reg.file == FIXED_GRF) {
305 } else if (reg.file == IMM) {
447 assert(inst->dst.file != UNIFORM && inst->dst.file != IMM);
463 if (inst->src[i].file == IMM)
466 const unsigned reg_size = inst->src[i].file == UNIFORM ? 4 : REG_SIZE;
479 if (inst->src[i].file != BAD_FILE &&
593 * the specified register file into a VGRF.
597 * destination in the register file: Gathering any number of portions from
601 is_copy_payload(brw_reg_file file, const fs_inst *inst)
605 inst->dst.file != VGRF)
609 if (inst->src[i].file != file ||
626 * contiguous block of registers from the given register file into the
630 is_identity_payload(brw_reg_file file, const fs_inst *inst) {
631 if (is_copy_payload(file, inst)) {