Lines Matching defs:dest
697 need_dest ? get_nir_dest(instr->dest.dest) : bld.null_reg_ud();
701 nir_dest_bit_size(instr->dest.dest)));
703 assert(!instr->dest.saturate);
742 assert(util_bitcount(instr->dest.write_mask) == 1);
743 channel = ffs(instr->dest.write_mask) - 1;
794 if (nir_dest_bit_size(instr->dest.dest) != 32 ||
853 assert(util_bitcount(instr->dest.write_mask) == 1);
854 channel = ffs(instr->dest.write_mask) - 1;
1024 instr->dest.dest.reg.reg == instr->src[i].src.reg.reg) {
1032 if (!(instr->dest.write_mask & (1 << i)))
1050 if (!(instr->dest.write_mask & (1 << i)))
1276 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1282 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1330 assert(nir_dest_bit_size(instr->dest.dest) == 32);
1355 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1361 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1362 if (nir_dest_bit_size(instr->dest.dest) == 32) {
1373 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1389 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1428 fs_reg dest = result;
1432 dest = bld.vgrf(op[0].type, 1);
1434 bld.CMP(dest, op[0], op[1], brw_cmod_for_nir_comparison(instr->op));
1437 bld.MOV(result, subscript(dest, BRW_REGISTER_TYPE_UD, 0));
1445 bld.MOV(retype(result, BRW_REGISTER_TYPE_D), retype(dest, src_type));
1456 fs_reg dest = result;
1460 dest = bld.vgrf(op[0].type, 1);
1462 bld.CMP(dest, op[0], op[1],
1466 bld.MOV(result, subscript(dest, BRW_REGISTER_TYPE_UD, 0));
1474 bld.MOV(retype(result, BRW_REGISTER_TYPE_D), retype(dest, src_type));
1501 nir_dest_bit_size(instr->dest.dest)));
1758 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1763 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1768 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1774 assert(nir_dest_bit_size(instr->dest.dest) == 32);
1779 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1801 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1830 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1834 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1838 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1969 if (nir_dest_bit_size(instr->dest.dest) == 64) {
2119 fs_visitor::get_nir_dest(const nir_dest &dest)
2121 if (dest.is_ssa) {
2123 brw_reg_type_from_bit_size(dest.ssa.bit_size,
2124 dest.ssa.bit_size == 8 ?
2127 nir_ssa_values[dest.ssa.index] =
2128 bld.vgrf(reg_type, dest.ssa.num_components);
2129 bld.UNDEF(nir_ssa_values[dest.ssa.index]);
2130 return nir_ssa_values[dest.ssa.index];
2133 assert(dest.reg.indirect == NULL);
2134 return offset(nir_locals[dest.reg.reg->index], bld,
2135 dest.reg.base_offset * dest.reg.reg->num_components);
2692 fs_reg dest;
2694 dest = get_nir_dest(instr->dest);
2702 assert(nir_dest_bit_size(instr->dest) == 32);
2703 fs_reg src = fs_reg(ATTR, nir_intrinsic_base(instr) * 4, dest.type);
2708 bld.MOV(offset(dest, bld, i), offset(src, bld, i));
2850 dst = get_nir_dest(instr->dest);
2913 assert(nir_dest_bit_size(instr->dest) == 32);
2987 assert(nir_dest_bit_size(instr->dest) == 32);
3117 fs_reg dest;
3119 dest = get_nir_dest(instr->dest);
3123 bld.MOV(dest, fs_reg(brw_vec1_grf(0, 1)));
3128 bld.MOV(offset(dest, bld, i), fs_reg(brw_vec8_grf(1 + i, 0)));
3134 assert(nir_dest_bit_size(instr->dest) == 32);
3146 fs_reg src = fs_reg(ATTR, imm_offset / 2, dest.type);
3149 bld.MOV(offset(dest, bld, i), component(src, comp));
3164 fs_reg tmp = bld.vgrf(dest.type, read_components);
3169 bld.MOV(offset(dest, bld, i),
3173 inst = bld.emit(SHADER_OPCODE_URB_READ_LOGICAL, dest,
3197 fs_reg tmp = bld.vgrf(dest.type, read_components);
3201 bld.MOV(offset(dest, bld, i),
3205 inst = bld.emit(SHADER_OPCODE_URB_READ_LOGICAL, dest,
3228 fs_reg dest;
3230 dest = get_nir_dest(instr->dest);
3236 bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD),
3244 emit_gs_input_load(dest, instr->src[0], instr->const_index[0],
3264 dest.type = val.type;
3265 bld.MOV(dest, val);
3450 fs_reg dest;
3452 dest = get_nir_dest(instr->dest);
3456 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D),
3464 dest.type = sample_pos.type;
3465 bld.MOV(dest, sample_pos);
3466 bld.MOV(offset(dest, bld, 1), offset(sample_pos, bld, 1));
3471 dest.type = BRW_REGISTER_TYPE_UD;
3472 bld.MOV(dest, fetch_render_target_array_index(bld));
3476 emit_is_helper_invocation(dest);
3486 dest.type = val.type;
3487 bld.MOV(dest, val);
3512 const fs_reg tmp = bld.vgrf(dest.type, 4);
3520 bld.MOV(offset(dest, bld, j),
3621 assert(nir_dest_bit_size(instr->dest) == 32);
3637 bld.MOV(offset(dest, bld, i),
3638 retype(component(per_primitive_reg(base), comp + i), dest.type));
3642 bld.MOV(offset(dest, bld, i),
3643 retype(component(interp_reg(base, comp + i), 3), dest.type));
3654 dest.type = BRW_REGISTER_TYPE_F;
3655 bld.MOV(offset(dest, bld, 0), component(interp, 3));
3656 bld.MOV(offset(dest, bld, 1), component(interp, 1));
3657 bld.MOV(offset(dest, bld, 2), component(interp, 0));
3668 bld.LOAD_PAYLOAD(dest, srcs, ARRAY_SIZE(srcs), 0);
3681 dest,
3696 dest,
3724 dest,
3752 dest,
3761 dest,
3770 emit_fragcoord_interpolation(dest);
3798 dest.type = BRW_REGISTER_TYPE_F;
3803 bld.MUL(offset(dest, bld, i), tmp, this->pixel_w);
3805 bld.emit(FS_OPCODE_LINTERP, offset(dest, bld, i), dst_xy, interp);
3824 fs_reg dest;
3826 dest = get_nir_dest(instr->dest);
3846 bld.AND(retype(dest, BRW_REGISTER_TYPE_UD),
3850 bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD), subgroup_id);
3858 dest.type = val.type;
3860 bld.MOV(offset(dest, bld, i), offset(val, bld, i));
3865 assert(nir_dest_bit_size(instr->dest) == 32);
3877 dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
3904 const unsigned bit_size = nir_dest_bit_size(instr->dest);
3911 /* Make dest unsigned because that's what the temporary will be */
3912 dest.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
3915 assert(nir_dest_bit_size(instr->dest) <= 32);
3917 if (nir_dest_bit_size(instr->dest) == 32 &&
3919 assert(nir_dest_num_components(instr->dest) <= 4);
3923 dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
3926 assert(nir_dest_num_components(instr->dest) == 1);
3932 bld.MOV(dest, subscript(read_result, dest.type, 0));
3986 bld.MOV(retype(offset(dest, bld, i), BRW_REGISTER_TYPE_UD),
4028 fs_reg dest;
4030 dest = get_nir_dest(instr->dest);
4034 bld.MOV(dest, retype(brw_vec1_grf(2, 0), dest.type));
4038 bld.MOV(dest, retype(brw_vec1_grf(2, 2), dest.type));
4042 fs_reg ud_dest = retype(dest, BRW_REGISTER_TYPE_UD);
4292 fs_reg dest;
4294 dest = get_nir_dest(instr->dest);
4361 dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
4393 dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
4433 for (unsigned c = 0; c < instr->dest.ssa.num_components; ++c) {
4434 bld.MOV(offset(retype(dest, tmp.type), bld, c),
4451 dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
4675 bld.LOAD_PAYLOAD(dest, srcs, ARRAY_SIZE(srcs), 0);
4681 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), brw_imm_d(1));
4687 dest, brw_imm_ud(id));
4696 instr->const_index[0] % type_sz(dest.type) == 0);
4698 fs_reg src(UNIFORM, instr->const_index[0] / 4, dest.type);
4702 assert(load_offset % type_sz(dest.type) == 0);
4709 bld.MOV(offset(dest, bld, j), offset(src, bld, j));
4721 instr->num_components * (int) type_sz(dest.type));
4723 (instr->num_components - 1) * type_sz(dest.type);
4728 if (type_sz(dest.type) != 8 || supports_64bit_indirects) {
4731 offset(dest, bld, j), offset(src, bld, j),
4736 type_sz(dest.type) / type_sz(BRW_REGISTER_TYPE_UD);
4745 subscript(offset(dest, bld, j), BRW_REGISTER_TYPE_UD, i),
4775 VARYING_PULL_CONSTANT_LOAD(bld, offset(dest, bld, i), surf_index,
4776 base_offset, i * type_sz(dest.type),
4777 nir_dest_bit_size(instr->dest) / 8);
4789 const unsigned type_size = type_sz(dest.type);
4804 push_reg = fs_reg(UNIFORM, UBO_START + i, dest.type);
4812 bld.MOV(offset(dest, bld, i),
4837 dest.type);
4840 bld.MOV(offset(dest, bld, c + d), component(consts, d));
4852 assert(nir_dest_bit_size(instr->dest) <= 32);
4860 if (nir_dest_bit_size(instr->dest) == 32 &&
4862 assert(nir_dest_num_components(instr->dest) <= 4);
4867 bld.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL, dest,
4872 const unsigned bit_size = nir_dest_bit_size(instr->dest);
4873 assert(nir_dest_num_components(instr->dest) == 1);
4880 bld.MOV(dest, subscript(tmp, dest.type, 0));
4944 assert(nir_dest_bit_size(instr->dest) == 32);
5000 bld.MOV(retype(offset(dest, bld, i), BRW_REGISTER_TYPE_UD),
5009 const unsigned bit_size = nir_dest_bit_size(instr->dest);
5017 /* Make dest unsigned because that's what the temporary will be */
5018 dest.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
5021 assert(nir_dest_bit_size(instr->dest) <= 32);
5023 if (nir_dest_bit_size(instr->dest) == 32 &&
5025 assert(nir_dest_num_components(instr->dest) <= 4);
5029 dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
5032 assert(nir_dest_num_components(instr->dest) == 1);
5038 bld.MOV(dest, subscript(read_result, dest.type, 0));
5172 bld.MOV(retype(dest, ret_payload.type), component(buffer_size, 0));
5179 assert(nir_dest_num_components(instr->dest) == 1);
5180 const unsigned bit_size = nir_dest_bit_size(instr->dest);
5201 /* Make dest unsigned because that's what the temporary will be */
5202 dest.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
5205 assert(nir_dest_num_components(instr->dest) == 1);
5206 assert(nir_dest_bit_size(instr->dest) <= 32);
5208 if (nir_dest_bit_size(instr->dest) == 32 &&
5211 assert(nir_dest_bit_size(instr->dest) == 32 &&
5219 dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
5226 dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
5235 bld.MOV(dest, read_result);
5291 dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
5321 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), brw_imm_d(dispatch_width));
5325 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D),
5365 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), component(res1, 0));
5397 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), component(res1, 0));
5438 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), component(res1, 0));
5458 if (instr->dest.ssa.bit_size > 32) {
5459 dest.type = BRW_REGISTER_TYPE_UQ;
5461 dest.type = BRW_REGISTER_TYPE_UD;
5463 bld.MOV(dest, flag);
5475 bld.MOV(retype(dest, value.type), fs_reg(component(tmp, 0)));
5481 bld.MOV(retype(dest, value.type), bld.emit_uniformize(value));
5489 bld.emit(SHADER_OPCODE_SHUFFLE, retype(dest, value.type), value, index);
5496 bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD),
5504 bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD),
5513 bld.emit(SHADER_OPCODE_CLUSTER_BROADCAST, retype(dest, value.type),
5531 bld.MOV(retype(dest, value.type), tmp);
5544 bld.MOV(retype(dest, value.type), tmp);
5556 bld.MOV(retype(dest, value.type), tmp);
5564 bld.emit(SHADER_OPCODE_SHUFFLE, retype(dest, value.type), value, idx);
5577 bld.MOV(retype(dest, value.type), tmp);
5585 bld.emit(SHADER_OPCODE_SHUFFLE, retype(dest, value.type), value, idx);
5614 dest.type = src.type;
5628 bld.group(group_size, i).MOV(horiz_offset(dest, i * group_size),
5632 bld.emit(SHADER_OPCODE_CLUSTER_BROADCAST, dest, scan,
5675 bld.MOV(retype(dest, src.type), scan);
5680 assert(nir_dest_bit_size(instr->dest) == 32);
5704 retype(byte_offset(dest, loaded * 4), BRW_REGISTER_TYPE_UD),
5754 assert(nir_dest_bit_size(instr->dest) == 32);
5781 retype(byte_offset(dest, loaded * 4), BRW_REGISTER_TYPE_UD),
5857 bld.SHR(retype(dest, BRW_REGISTER_TYPE_UD), raw_id, brw_imm_ud(9));
5862 fs_reg dst = retype(dest, BRW_REGISTER_TYPE_UD);
5920 bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD),
6004 assert(nir_dest_bit_size(instr->dest) == 32 ||
6005 (nir_dest_bit_size(instr->dest) == 64 && devinfo->has_lsc));
6007 fs_reg dest;
6009 dest = get_nir_dest(instr->dest);
6033 dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
6040 fs_reg dest;
6042 dest = get_nir_dest(instr->dest);
6063 dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
6070 fs_reg dest;
6072 dest = get_nir_dest(instr->dest);
6105 dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
6112 fs_reg dest;
6114 dest = get_nir_dest(instr->dest);
6145 dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
6164 fs_reg dest;
6166 dest = get_nir_dest(instr->dest);
6190 switch (nir_dest_bit_size(instr->dest)) {
6195 bld.MOV(retype(dest, BRW_REGISTER_TYPE_UW), dest32);
6199 bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL, dest,
6203 bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL, dest,
6216 fs_reg dest = get_nir_dest(instr->dest);
6239 switch (nir_dest_bit_size(instr->dest)) {
6244 bld.MOV(retype(dest, BRW_REGISTER_TYPE_UW), dest32);
6248 bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL, dest,
6252 bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL, dest,
6464 fs_reg dst = retype(get_nir_dest(instr->dest), BRW_REGISTER_TYPE_D);
6505 unsigned write_mask = instr->dest.is_ssa ?
6506 nir_ssa_def_components_read(&instr->dest.ssa):
6547 bld.LOAD_PAYLOAD(get_nir_dest(instr->dest), nir_dest, dest_size, 0);