Lines Matching defs:dst
267 emit(enum opcode opcode, const dst_reg &dst) const
269 return emit(instruction(opcode, dispatch_width(), dst));
276 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0) const
286 return emit(instruction(opcode, dispatch_width(), dst,
290 return emit(instruction(opcode, dispatch_width(), dst, src0));
298 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
305 return emit(instruction(opcode, dispatch_width(), dst,
310 return emit(instruction(opcode, dispatch_width(), dst,
320 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
328 return emit(instruction(opcode, dispatch_width(), dst,
334 return emit(instruction(opcode, dispatch_width(), dst,
344 emit(enum opcode opcode, const dst_reg &dst, const src_reg srcs[],
351 return emit(opcode, dst, srcs[0], srcs[1]);
353 return emit(opcode, dst, srcs[0], srcs[1], srcs[2]);
355 return emit(instruction(opcode, dispatch_width(), dst, srcs, n));
389 emit_minmax(const dst_reg &dst, const src_reg &src0,
397 return set_condmod(mod, SEL(dst, fix_unsigned_negate(src0),
407 /* FIXME: We use a vector chan_index and dst to allow constant and
416 const dst_reg dst = vgrf(src.type);
419 ubld.emit(SHADER_OPCODE_BROADCAST, dst, src, component(chan_index, 0));
421 return src_reg(component(dst, 0));
431 const dst_reg dst = vgrf(src.type, num_components);
432 LOAD_PAYLOAD(dst, src_comps, num_components, 0);
436 return src_reg(dst);
574 op(const dst_reg &dst, const src_reg &src0) const \
576 return emit(BRW_OPCODE_##op, dst, src0); \
581 op(const dst_reg &dst, const src_reg &src0, const src_reg &src1) const \
583 return emit(BRW_OPCODE_##op, dst, src0, src1); \
588 op(const dst_reg &dst, const src_reg &src0, const src_reg &src1) const \
590 instruction *inst = emit(BRW_OPCODE_##op, dst, src0, src1); \
597 op(const dst_reg &dst, const src_reg &src0, const src_reg &src1, \
600 return emit(BRW_OPCODE_##op, dst, src0, src1, src2); \
661 CMP(const dst_reg &dst, const src_reg &src0, const src_reg &src1,
677 emit(BRW_OPCODE_CMP, retype(dst, src0.type),
686 CMPN(const dst_reg &dst, const src_reg &src0, const src_reg &src1,
702 emit(BRW_OPCODE_CMPN, retype(dst, src0.type),
717 * CSEL: dst = src2 <op> 0.0f ? src0 : src1
720 CSEL(const dst_reg &dst, const src_reg &src0, const src_reg &src1,
731 retype(dst, BRW_REGISTER_TYPE_F),
741 LRP(const dst_reg &dst, const src_reg &x, const src_reg &y,
748 return emit(BRW_OPCODE_LRP, dst, a, y, x);
752 const dst_reg y_times_a = vgrf(dst.type);
753 const dst_reg one_minus_a = vgrf(dst.type);
754 const dst_reg x_times_one_minus_a = vgrf(dst.type);
759 return ADD(dst, src_reg(x_times_one_minus_a), src_reg(y_times_a));
767 LOAD_PAYLOAD(const dst_reg &dst, const src_reg *src,
770 instruction *inst = emit(SHADER_OPCODE_LOAD_PAYLOAD, dst, src, sources);
775 dst.stride;
782 UNDEF(const dst_reg &dst) const
784 assert(dst.file == VGRF);
786 retype(dst, BRW_REGISTER_TYPE_UD));
787 inst->size_written = shader->alloc.sizes[dst.nr] * REG_SIZE;