Lines Matching refs:one
333 * code generator: if src == dst and one instruction writes the
352 * that one of the instructions will read from a channel corresponding
618 * During a compile of dispatch width greater than n (if one happens anyway),
1215 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1241 * this task in only one instruction:
1293 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1454 fs_reg one = vgrf(glsl_type::int_type);
1456 abld.MOV(one, brw_imm_d(1));
1457 abld.SHL(enabled_mask, one, nir_system_values[SYSTEM_VALUE_SAMPLE_ID]);
1583 /* With COMPUTE_WALKER, we can push up to one register worth of data via
1906 /* Re-compute the VUE map here in the case that the one coming from
1907 * geometry has more than one position slot (used for Primitive
2208 /* The first one should always be 0 as a quick sanity check. */
2235 /* The last one gets the original register number */
2499 const unsigned block_sz = 64; /* Fetch one cacheline at a time. */
2927 * sources switch from one VGRF to a different one.
3145 /* If this one instruction didn't populate all the
3154 * would need us to understand coalescing out more than one MOV at
3726 * mask, since a later instruction will use one of the result channels as a
3764 * one of the other components for the extended descriptor
3948 * do 32-bit integer multiplication in one instruction, but instead
4151 /* Until Gfx8, integer multiplies read 32-bits from one source,
4562 * which is the one that is going to limit the overall execution size of
5013 /* Only one execution size is representable pre-ILK depending on whether
5184 /* If the instruction writes more than one component we'll have to shuffle
5208 * group which could cause one of the lowered instructions to overwrite
5340 * is considered valid when at least one sample is enabled. For
5348 * next one must send Slot[15:8]."
6169 * one more time to clean those up if they exist.
6229 /* Only one register left; do SIMD8 */
6400 * the first one in the program closes the region of divergent
6854 * Instead of enabling push constants one can alternatively enable one of the
6855 * inputs. Here one simply chooses "layer" which shouldn't impose much
7545 * Instead, we just give them exactly one shader and we pick the widest one
7561 /* Iron lake and earlier only have one Dispatch GRF start field. Make
7578 * are those in which only one dispatch width is enabled.
7742 /* If the whole workgroup fits in one thread, we can lower subgroup_id
8087 /* We only have one constant data so we want to make sure they're all the