Lines Matching refs:subnr
118 assert(dest.subnr == 0);
132 assert(dest.subnr % 16 == 0);
137 brw_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16);
147 brw_inst_set_dst_da1_subreg_nr(devinfo, inst, dest.subnr);
152 brw_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16);
165 brw_inst_set_dst_ia_subreg_nr(devinfo, inst, dest.subnr);
239 assert(reg.subnr == 0);
251 assert(reg.subnr % 16 == 0);
257 brw_inst_set_src0_da16_subreg_nr(devinfo, inst, reg.subnr / 16);
284 brw_inst_set_src0_da1_subreg_nr(devinfo, inst, reg.subnr);
286 brw_inst_set_src0_da16_subreg_nr(devinfo, inst, reg.subnr / 16);
289 brw_inst_set_src0_ia_subreg_nr(devinfo, inst, reg.subnr);
360 assert(reg.subnr == 0);
400 brw_inst_set_src1_da1_subreg_nr(devinfo, inst, reg.subnr);
402 brw_inst_set_src1_da16_subreg_nr(devinfo, inst, reg.subnr / 16);
761 return reg.subnr / 4;
846 brw_inst_set_3src_a1_dst_subreg_nr(devinfo, inst, dest.subnr / 8);
870 brw_inst_set_3src_a1_src0_subreg_nr(devinfo, inst, src0.subnr);
884 brw_inst_set_3src_a1_src1_subreg_nr(devinfo, inst, src1.subnr);
899 brw_inst_set_3src_a1_src2_subreg_nr(devinfo, inst, src2.subnr);
956 brw_inst_set_3src_a16_dst_subreg_nr(devinfo, inst, dest.subnr / 4);
2837 assert(desc.subnr == 0);
2847 assert((ex_desc.subnr & 0x3) == 0);
2849 brw_inst_set_send_ex_desc_ia_subreg_nr(devinfo, send, ex_desc.subnr >> 2);
3499 assert(src.subnr == 0);
3504 unsigned offset = src.nr * REG_SIZE + src.subnr;
3549 retype(brw_vec1_indirect(addr.subnr, offset),
3553 retype(brw_vec1_indirect(addr.subnr, offset + 4),
3557 retype(brw_vec1_indirect(addr.subnr, offset), src.type));