Lines Matching defs:src0
370 * "Accumulator registers may be accessed explicitly as src0
741 struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
744 assert(src0.file != BRW_IMMEDIATE_VALUE || type_sz(src0.type) <= 4);
749 brw_set_src0(p, insn, src0);
807 struct brw_reg src0, struct brw_reg src1, struct brw_reg src2)
817 assert(!(src0.file == BRW_IMMEDIATE_VALUE &&
820 assert(src0.file == BRW_IMMEDIATE_VALUE || src0.nr < 128);
824 assert(src0.address_mode == BRW_ADDRESS_DIRECT);
859 brw_inst_set_3src_a1_src0_type(devinfo, inst, src0.type);
863 if (src0.file == BRW_IMMEDIATE_VALUE) {
864 brw_inst_set_3src_a1_src0_imm(devinfo, inst, src0.ud);
867 devinfo, inst, to_3src_align1_vstride(devinfo, src0.vstride));
869 to_3src_align1_hstride(src0.hstride));
870 brw_inst_set_3src_a1_src0_subreg_nr(devinfo, inst, src0.subnr);
871 if (src0.type == BRW_REGISTER_TYPE_NF) {
874 brw_inst_set_3src_src0_reg_nr(devinfo, inst, src0.nr);
876 brw_inst_set_3src_src0_abs(devinfo, inst, src0.abs);
877 brw_inst_set_3src_src0_negate(devinfo, inst, src0.negate);
905 assert(src0.file == BRW_GENERAL_REGISTER_FILE ||
906 src0.file == BRW_IMMEDIATE_VALUE ||
907 (src0.file == BRW_ARCHITECTURE_REGISTER_FILE &&
908 src0.type == BRW_REGISTER_TYPE_NF));
915 if (src0.file == BRW_IMMEDIATE_VALUE) {
918 brw_inst_set_3src_a1_src0_reg_file(devinfo, inst, src0.file);
930 src0.file == BRW_GENERAL_REGISTER_FILE ?
959 assert(src0.file == BRW_GENERAL_REGISTER_FILE);
960 brw_inst_set_3src_a16_src0_swizzle(devinfo, inst, src0.swizzle);
961 brw_inst_set_3src_a16_src0_subreg_nr(devinfo, inst, get_3src_subreg_nr(src0));
962 brw_inst_set_3src_src0_reg_nr(devinfo, inst, src0.nr);
963 brw_inst_set_3src_src0_abs(devinfo, inst, src0.abs);
964 brw_inst_set_3src_src0_negate(devinfo, inst, src0.negate);
966 src0.vstride == BRW_VERTICAL_STRIDE_0);
1024 struct brw_reg src0) \
1026 return brw_alu1(p, BRW_OPCODE_##OP, dest, src0); \
1032 struct brw_reg src0, \
1035 return brw_alu2(p, BRW_OPCODE_##OP, dest, src0, src1); \
1041 struct brw_reg src0, \
1046 if (src0.vstride == BRW_VERTICAL_STRIDE_0) \
1047 src0.swizzle = BRW_SWIZZLE_XXXX; \
1053 return brw_alu3(p, BRW_OPCODE_##OP, dest, src0, src1, src2); \
1059 struct brw_reg src0, \
1066 assert(src0.type == BRW_REGISTER_TYPE_F); \
1070 assert(src0.type == BRW_REGISTER_TYPE_DF); \
1076 if (src0.vstride == BRW_VERTICAL_STRIDE_0) \
1077 src0.swizzle = BRW_SWIZZLE_XXXX; \
1083 return brw_alu3(p, BRW_OPCODE_##OP, dest, src0, src1, src2); \
1125 brw_MOV(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0)
1136 (src0.type == BRW_REGISTER_TYPE_F ||
1137 src0.type == BRW_REGISTER_TYPE_D ||
1138 src0.type == BRW_REGISTER_TYPE_UD) &&
1139 !has_scalar_region(src0)) {
1140 assert(src0.vstride == src0.width + src0.hstride);
1141 src0.vstride = src0.hstride;
1142 src0.width = BRW_WIDTH_2;
1143 src0.hstride = BRW_HORIZONTAL_STRIDE_0;
1146 return brw_alu1(p, BRW_OPCODE_MOV, dest, src0);
1151 struct brw_reg src0, struct brw_reg src1)
1154 if (src0.type == BRW_REGISTER_TYPE_F ||
1155 (src0.file == BRW_IMMEDIATE_VALUE &&
1156 src0.type == BRW_REGISTER_TYPE_VF)) {
1164 assert(src0.type != BRW_REGISTER_TYPE_UD);
1165 assert(src0.type != BRW_REGISTER_TYPE_D);
1168 return brw_alu2(p, BRW_OPCODE_ADD, dest, src0, src1);
1173 struct brw_reg src0, struct brw_reg src1)
1175 assert(dest.type == src0.type);
1176 assert(src0.type == src1.type);
1177 switch (src0.type) {
1189 return brw_alu2(p, BRW_OPCODE_AVG, dest, src0, src1);
1194 struct brw_reg src0, struct brw_reg src1)
1197 if (src0.type == BRW_REGISTER_TYPE_D ||
1198 src0.type == BRW_REGISTER_TYPE_UD ||
1204 if (src0.type == BRW_REGISTER_TYPE_F ||
1205 (src0.file == BRW_IMMEDIATE_VALUE &&
1206 src0.type == BRW_REGISTER_TYPE_VF)) {
1214 assert(src0.type != BRW_REGISTER_TYPE_UD);
1215 assert(src0.type != BRW_REGISTER_TYPE_D);
1218 assert(src0.file != BRW_ARCHITECTURE_REGISTER_FILE ||
1219 src0.nr != BRW_ARF_ACCUMULATOR);
1223 return brw_alu2(p, BRW_OPCODE_MUL, dest, src0, src1);
1228 struct brw_reg src0, struct brw_reg src1)
1230 src0.vstride = BRW_VERTICAL_STRIDE_0;
1231 src0.width = BRW_WIDTH_1;
1232 src0.hstride = BRW_HORIZONTAL_STRIDE_0;
1233 return brw_alu2(p, BRW_OPCODE_LINE, dest, src0, src1);
1238 struct brw_reg src0, struct brw_reg src1)
1240 src0.vstride = BRW_VERTICAL_STRIDE_0;
1241 src0.width = BRW_WIDTH_1;
1242 src0.hstride = BRW_HORIZONTAL_STRIDE_0;
1246 return brw_alu2(p, BRW_OPCODE_PLN, dest, src0, src1);
1471 struct brw_reg src0, struct brw_reg src1)
1481 brw_set_src0(p, insn, src0);
1807 * and <src0> locations.
1987 struct brw_reg src0,
1995 brw_set_src0(p, insn, src0);
2016 struct brw_reg src0,
2024 brw_set_src0(p, insn, src0);
2086 struct brw_reg src0,
2099 assert(src0.hstride == BRW_HORIZONTAL_STRIDE_1);
2106 assert(src0.type != BRW_REGISTER_TYPE_F);
2113 assert(!src0.negate);
2114 assert(!src0.abs);
2118 assert(src0.type == BRW_REGISTER_TYPE_F ||
2119 (src0.type == BRW_REGISTER_TYPE_HF && devinfo->ver >= 9));
2126 assert(!src0.negate);
2127 assert(!src0.abs);
2135 brw_set_src0(p, insn, src0);
2467 struct brw_reg dest, src0;
2484 src0 = payload;
2488 src0 = implied_header;
2492 brw_set_src0(p, insn, src0);
2538 struct brw_reg src0,
2552 gfx6_resolve_implied_move(p, &src0, msg_reg_nr);
2576 brw_set_src0(p, insn, src0);
2640 struct brw_reg src0,
2650 gfx6_resolve_implied_move(p, &src0, msg_reg_nr);
2670 brw_set_src0(p, insn, src0);
3063 struct brw_reg src0,
3071 gfx6_resolve_implied_move(p, &src0, msg_reg_nr);
3075 brw_set_src0(p, insn, src0);
3103 struct brw_reg src0,
3112 gfx6_resolve_implied_move(p, &src0, msg_reg_nr);
3117 brw_set_src0(p, insn, src0);