Lines Matching defs:devinfo
50 const struct intel_device_info *devinfo = p->devinfo;
51 if (devinfo->ver < 6)
58 assert(devinfo->ver < 12);
81 const struct intel_device_info *devinfo = p->devinfo;
82 if (devinfo->ver >= 7 && reg->file == BRW_MESSAGE_REGISTER_FILE) {
91 const struct intel_device_info *devinfo = p->devinfo;
94 assert((dest.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver));
112 if (devinfo->ver >= 12 &&
119 assert(brw_inst_exec_size(devinfo, inst) == BRW_EXECUTE_1 ||
123 brw_inst_set_dst_reg_file(devinfo, inst, dest.file);
124 brw_inst_set_dst_da_reg_nr(devinfo, inst, dest.nr);
128 assert(devinfo->ver < 12);
136 brw_inst_set_dst_da_reg_nr(devinfo, inst, dest.nr);
137 brw_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16);
138 brw_inst_set_send_dst_reg_file(devinfo, inst, dest.file);
140 brw_inst_set_dst_file_type(devinfo, inst, dest.file, dest.type);
141 brw_inst_set_dst_address_mode(devinfo, inst, dest.address_mode);
144 brw_inst_set_dst_da_reg_nr(devinfo, inst, dest.nr);
146 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
147 brw_inst_set_dst_da1_subreg_nr(devinfo, inst, dest.subnr);
150 brw_inst_set_dst_hstride(devinfo, inst, dest.hstride);
152 brw_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16);
153 brw_inst_set_da16_writemask(devinfo, inst, dest.writemask);
162 brw_inst_set_dst_hstride(devinfo, inst, 1);
165 brw_inst_set_dst_ia_subreg_nr(devinfo, inst, dest.subnr);
169 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
170 brw_inst_set_dst_ia1_addr_imm(devinfo, inst,
174 brw_inst_set_dst_hstride(devinfo, inst, dest.hstride);
176 brw_inst_set_dst_ia16_addr_imm(devinfo, inst,
179 brw_inst_set_dst_hstride(devinfo, inst, 1);
198 if (devinfo->ver >= 6)
204 brw_inst_set_exec_size(devinfo, inst, dest.width);
211 const struct intel_device_info *devinfo = p->devinfo;
214 assert((reg.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver));
220 if (devinfo->ver >= 6 &&
234 if (devinfo->ver >= 12 &&
244 brw_inst_set_send_src0_reg_file(devinfo, inst, reg.file);
245 brw_inst_set_src0_da_reg_nr(devinfo, inst, reg.nr);
256 brw_inst_set_src0_da_reg_nr(devinfo, inst, reg.nr);
257 brw_inst_set_src0_da16_subreg_nr(devinfo, inst, reg.subnr / 16);
259 brw_inst_set_src0_file_type(devinfo, inst, reg.file, reg.type);
260 brw_inst_set_src0_abs(devinfo, inst, reg.abs);
261 brw_inst_set_src0_negate(devinfo, inst, reg.negate);
262 brw_inst_set_src0_address_mode(devinfo, inst, reg.address_mode);
267 brw_inst_set_imm_df(devinfo, inst, reg.df);
270 brw_inst_set_imm_uq(devinfo, inst, reg.u64);
272 brw_inst_set_imm_ud(devinfo, inst, reg.ud);
274 if (devinfo->ver < 12 && type_sz(reg.type) < 8) {
275 brw_inst_set_src1_reg_file(devinfo, inst,
277 brw_inst_set_src1_reg_hw_type(devinfo, inst,
278 brw_inst_src0_reg_hw_type(devinfo, inst));
282 brw_inst_set_src0_da_reg_nr(devinfo, inst, reg.nr);
283 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
284 brw_inst_set_src0_da1_subreg_nr(devinfo, inst, reg.subnr);
286 brw_inst_set_src0_da16_subreg_nr(devinfo, inst, reg.subnr / 16);
289 brw_inst_set_src0_ia_subreg_nr(devinfo, inst, reg.subnr);
291 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
292 brw_inst_set_src0_ia1_addr_imm(devinfo, inst, reg.indirect_offset);
294 brw_inst_set_src0_ia16_addr_imm(devinfo, inst, reg.indirect_offset);
298 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
300 brw_inst_exec_size(devinfo, inst) == BRW_EXECUTE_1) {
301 brw_inst_set_src0_hstride(devinfo, inst, BRW_HORIZONTAL_STRIDE_0);
302 brw_inst_set_src0_width(devinfo, inst, BRW_WIDTH_1);
303 brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_0);
305 brw_inst_set_src0_hstride(devinfo, inst, reg.hstride);
306 brw_inst_set_src0_width(devinfo, inst, reg.width);
307 brw_inst_set_src0_vstride(devinfo, inst, reg.vstride);
310 brw_inst_set_src0_da16_swiz_x(devinfo, inst,
312 brw_inst_set_src0_da16_swiz_y(devinfo, inst,
314 brw_inst_set_src0_da16_swiz_z(devinfo, inst,
316 brw_inst_set_src0_da16_swiz_w(devinfo, inst,
323 brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
324 } else if (devinfo->verx10 == 70 &&
334 brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
336 brw_inst_set_src0_vstride(devinfo, inst, reg.vstride);
347 const struct intel_device_info *devinfo = p->devinfo;
354 (devinfo->ver >= 12 &&
365 brw_inst_set_send_src1_reg_nr(devinfo, inst, reg.nr);
366 brw_inst_set_send_src1_reg_file(devinfo, inst, reg.file);
379 brw_inst_set_src1_file_type(devinfo, inst, reg.file, reg.type);
380 brw_inst_set_src1_abs(devinfo, inst, reg.abs);
381 brw_inst_set_src1_negate(devinfo, inst, reg.negate);
385 assert(brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE);
390 brw_inst_set_imm_ud(devinfo, inst, reg.ud);
398 brw_inst_set_src1_da_reg_nr(devinfo, inst, reg.nr);
399 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
400 brw_inst_set_src1_da1_subreg_nr(devinfo, inst, reg.subnr);
402 brw_inst_set_src1_da16_subreg_nr(devinfo, inst, reg.subnr / 16);
405 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
407 brw_inst_exec_size(devinfo, inst) == BRW_EXECUTE_1) {
408 brw_inst_set_src1_hstride(devinfo, inst, BRW_HORIZONTAL_STRIDE_0);
409 brw_inst_set_src1_width(devinfo, inst, BRW_WIDTH_1);
410 brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_0);
412 brw_inst_set_src1_hstride(devinfo, inst, reg.hstride);
413 brw_inst_set_src1_width(devinfo, inst, reg.width);
414 brw_inst_set_src1_vstride(devinfo, inst, reg.vstride);
417 brw_inst_set_src1_da16_swiz_x(devinfo, inst,
419 brw_inst_set_src1_da16_swiz_y(devinfo, inst,
421 brw_inst_set_src1_da16_swiz_z(devinfo, inst,
423 brw_inst_set_src1_da16_swiz_w(devinfo, inst,
430 brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
431 } else if (devinfo->verx10 == 70 &&
441 brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
443 brw_inst_set_src1_vstride(devinfo, inst, reg.vstride);
458 const struct intel_device_info *devinfo = p->devinfo;
461 if (devinfo->ver < 12)
462 brw_inst_set_src1_file_type(devinfo, inst,
464 brw_inst_set_send_desc(devinfo, inst, desc);
465 if (devinfo->ver >= 9)
466 brw_inst_set_send_ex_desc(devinfo, inst, ex_desc);
476 const struct intel_device_info *devinfo = p->devinfo;
505 devinfo, msg_length, response_length, false));
507 brw_inst_set_sfid(devinfo, inst, BRW_SFID_MATH);
508 brw_inst_set_math_msg_function(devinfo, inst, function);
509 brw_inst_set_math_msg_signed_int(devinfo, inst, integer_type);
510 brw_inst_set_math_msg_precision(devinfo, inst, low_precision);
511 brw_inst_set_math_msg_saturate(devinfo, inst, brw_inst_saturate(devinfo, inst));
512 brw_inst_set_math_msg_data_type(devinfo, inst, dataType);
513 brw_inst_set_saturate(devinfo, inst, 0);
523 const struct intel_device_info *devinfo = p->devinfo;
526 devinfo, 1, response_length, true));
528 brw_inst_set_sfid(devinfo, insn, BRW_SFID_URB);
529 brw_inst_set_eot(devinfo, insn, end_of_thread);
530 brw_inst_set_urb_opcode(devinfo, insn, 1); /* FF_SYNC */
531 brw_inst_set_urb_allocate(devinfo, insn, allocate);
533 brw_inst_set_urb_global_offset(devinfo, insn, 0);
534 brw_inst_set_urb_swizzle_control(devinfo, insn, 0);
535 brw_inst_set_urb_used(devinfo, insn, 0);
536 brw_inst_set_urb_complete(devinfo, insn, 0);
547 const struct intel_device_info *devinfo = p->devinfo;
549 assert(devinfo->ver < 7 || swizzle_control != BRW_URB_SWIZZLE_TRANSPOSE);
550 assert(devinfo->ver < 7 || !(flags & BRW_URB_WRITE_ALLOCATE));
551 assert(devinfo->ver >= 7 || !(flags & BRW_URB_WRITE_PER_SLOT_OFFSET));
554 devinfo, msg_length, response_length, true));
556 brw_inst_set_sfid(devinfo, insn, BRW_SFID_URB);
557 brw_inst_set_eot(devinfo, insn, !!(flags & BRW_URB_WRITE_EOT));
561 brw_inst_set_urb_opcode(devinfo, insn, BRW_URB_OPCODE_WRITE_OWORD);
563 brw_inst_set_urb_opcode(devinfo, insn, BRW_URB_OPCODE_WRITE_HWORD);
566 brw_inst_set_urb_global_offset(devinfo, insn, offset);
567 brw_inst_set_urb_swizzle_control(devinfo, insn, swizzle_control);
569 if (devinfo->ver < 8) {
570 brw_inst_set_urb_complete(devinfo, insn, !!(flags & BRW_URB_WRITE_COMPLETE));
573 if (devinfo->ver < 7) {
574 brw_inst_set_urb_allocate(devinfo, insn, !!(flags & BRW_URB_WRITE_ALLOCATE));
575 brw_inst_set_urb_used(devinfo, insn, !(flags & BRW_URB_WRITE_UNUSED));
577 brw_inst_set_urb_per_slot_offset(devinfo, insn,
594 const struct intel_device_info *devinfo = p->devinfo;
596 (devinfo->ver >= 8 && num_regs == 8));
597 const unsigned block_size = (devinfo->ver >= 8 ? util_logbase2(num_regs) :
601 devinfo, mlen, rlen, header_present));
603 brw_inst_set_sfid(devinfo, inst, GFX7_SFID_DATAPORT_DATA_CACHE);
604 brw_inst_set_dp_category(devinfo, inst, 1); /* Scratch Block Read/Write msgs */
605 brw_inst_set_scratch_read_write(devinfo, inst, write);
606 brw_inst_set_scratch_type(devinfo, inst, dword);
607 brw_inst_set_scratch_invalidate_after_read(devinfo, inst, invalidate_after_read);
608 brw_inst_set_scratch_block_size(devinfo, inst, block_size);
609 brw_inst_set_scratch_addr_offset(devinfo, inst, addr_offset);
617 const struct intel_device_info *devinfo = isa->devinfo;
619 brw_inst_set_exec_size(devinfo, insn, state->exec_size);
620 brw_inst_set_group(devinfo, insn, state->group);
621 brw_inst_set_compression(devinfo, insn, state->compressed);
622 brw_inst_set_access_mode(devinfo, insn, state->access_mode);
623 brw_inst_set_mask_control(devinfo, insn, state->mask_control);
624 if (devinfo->ver >= 12)
625 brw_inst_set_swsb(devinfo, insn, tgl_swsb_encode(devinfo, state->swsb));
626 brw_inst_set_saturate(devinfo, insn, state->saturate);
627 brw_inst_set_pred_control(devinfo, insn, state->predicate);
628 brw_inst_set_pred_inv(devinfo, insn, state->pred_inv);
632 brw_inst_set_3src_a16_flag_subreg_nr(devinfo, insn, state->flag_subreg % 2);
633 if (devinfo->ver >= 7)
634 brw_inst_set_3src_a16_flag_reg_nr(devinfo, insn, state->flag_subreg / 2);
636 brw_inst_set_flag_subreg_nr(devinfo, insn, state->flag_subreg % 2);
637 if (devinfo->ver >= 7)
638 brw_inst_set_flag_reg_nr(devinfo, insn, state->flag_subreg / 2);
641 if (devinfo->ver >= 6)
642 brw_inst_set_acc_wr_control(devinfo, insn, state->acc_wr_control);
765 to_3src_align1_vstride(const struct intel_device_info *devinfo,
772 assert(devinfo->ver >= 12);
775 assert(devinfo->ver < 12);
809 const struct intel_device_info *devinfo = p->devinfo;
816 if (devinfo->ver >= 10)
828 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
832 if (devinfo->ver >= 12) {
833 brw_inst_set_3src_a1_dst_reg_file(devinfo, inst, dest.file);
834 brw_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr);
837 brw_inst_set_3src_a1_dst_reg_file(devinfo, inst,
839 brw_inst_set_3src_dst_reg_nr(devinfo, inst, BRW_ARF_ACCUMULATOR);
841 brw_inst_set_3src_a1_dst_reg_file(devinfo, inst,
843 brw_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr);
846 brw_inst_set_3src_a1_dst_subreg_nr(devinfo, inst, dest.subnr / 8);
848 brw_inst_set_3src_a1_dst_hstride(devinfo, inst, BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1);
851 brw_inst_set_3src_a1_exec_type(devinfo, inst,
854 brw_inst_set_3src_a1_exec_type(devinfo, inst,
858 brw_inst_set_3src_a1_dst_type(devinfo, inst, dest.type);
859 brw_inst_set_3src_a1_src0_type(devinfo, inst, src0.type);
860 brw_inst_set_3src_a1_src1_type(devinfo, inst, src1.type);
861 brw_inst_set_3src_a1_src2_type(devinfo, inst, src2.type);
864 brw_inst_set_3src_a1_src0_imm(devinfo, inst, src0.ud);
867 devinfo, inst, to_3src_align1_vstride(devinfo, src0.vstride));
868 brw_inst_set_3src_a1_src0_hstride(devinfo, inst,
870 brw_inst_set_3src_a1_src0_subreg_nr(devinfo, inst, src0.subnr);
872 brw_inst_set_3src_src0_reg_nr(devinfo, inst, BRW_ARF_ACCUMULATOR);
874 brw_inst_set_3src_src0_reg_nr(devinfo, inst, src0.nr);
876 brw_inst_set_3src_src0_abs(devinfo, inst, src0.abs);
877 brw_inst_set_3src_src0_negate(devinfo, inst, src0.negate);
880 devinfo, inst, to_3src_align1_vstride(devinfo, src1.vstride));
881 brw_inst_set_3src_a1_src1_hstride(devinfo, inst,
884 brw_inst_set_3src_a1_src1_subreg_nr(devinfo, inst, src1.subnr);
886 brw_inst_set_3src_src1_reg_nr(devinfo, inst, BRW_ARF_ACCUMULATOR);
888 brw_inst_set_3src_src1_reg_nr(devinfo, inst, src1.nr);
890 brw_inst_set_3src_src1_abs(devinfo, inst, src1.abs);
891 brw_inst_set_3src_src1_negate(devinfo, inst, src1.negate);
894 brw_inst_set_3src_a1_src2_imm(devinfo, inst, src2.ud);
896 brw_inst_set_3src_a1_src2_hstride(devinfo, inst,
899 brw_inst_set_3src_a1_src2_subreg_nr(devinfo, inst, src2.subnr);
900 brw_inst_set_3src_src2_reg_nr(devinfo, inst, src2.nr);
901 brw_inst_set_3src_src2_abs(devinfo, inst, src2.abs);
902 brw_inst_set_3src_src2_negate(devinfo, inst, src2.negate);
914 if (devinfo->ver >= 12) {
916 brw_inst_set_3src_a1_src0_is_imm(devinfo, inst, 1);
918 brw_inst_set_3src_a1_src0_reg_file(devinfo, inst, src0.file);
921 brw_inst_set_3src_a1_src1_reg_file(devinfo, inst, src1.file);
924 brw_inst_set_3src_a1_src2_is_imm(devinfo, inst, 1);
926 brw_inst_set_3src_a1_src2_reg_file(devinfo, inst, src2.file);
929 brw_inst_set_3src_a1_src0_reg_file(devinfo, inst,
933 brw_inst_set_3src_a1_src1_reg_file(devinfo, inst,
937 brw_inst_set_3src_a1_src2_reg_file(devinfo, inst,
950 (dest.type == BRW_REGISTER_TYPE_HF && devinfo->ver >= 8));
951 if (devinfo->ver == 6) {
952 brw_inst_set_3src_a16_dst_reg_file(devinfo, inst,
955 brw_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr);
956 brw_inst_set_3src_a16_dst_subreg_nr(devinfo, inst, dest.subnr / 4);
957 brw_inst_set_3src_a16_dst_writemask(devinfo, inst, dest.writemask);
960 brw_inst_set_3src_a16_src0_swizzle(devinfo, inst, src0.swizzle);
961 brw_inst_set_3src_a16_src0_subreg_nr(devinfo, inst, get_3src_subreg_nr(src0));
962 brw_inst_set_3src_src0_reg_nr(devinfo, inst, src0.nr);
963 brw_inst_set_3src_src0_abs(devinfo, inst, src0.abs);
964 brw_inst_set_3src_src0_negate(devinfo, inst, src0.negate);
965 brw_inst_set_3src_a16_src0_rep_ctrl(devinfo, inst,
969 brw_inst_set_3src_a16_src1_swizzle(devinfo, inst, src1.swizzle);
970 brw_inst_set_3src_a16_src1_subreg_nr(devinfo, inst, get_3src_subreg_nr(src1));
971 brw_inst_set_3src_src1_reg_nr(devinfo, inst, src1.nr);
972 brw_inst_set_3src_src1_abs(devinfo, inst, src1.abs);
973 brw_inst_set_3src_src1_negate(devinfo, inst, src1.negate);
974 brw_inst_set_3src_a16_src1_rep_ctrl(devinfo, inst,
978 brw_inst_set_3src_a16_src2_swizzle(devinfo, inst, src2.swizzle);
979 brw_inst_set_3src_a16_src2_subreg_nr(devinfo, inst, get_3src_subreg_nr(src2));
980 brw_inst_set_3src_src2_reg_nr(devinfo, inst, src2.nr);
981 brw_inst_set_3src_src2_abs(devinfo, inst, src2.abs);
982 brw_inst_set_3src_src2_negate(devinfo, inst, src2.negate);
983 brw_inst_set_3src_a16_src2_rep_ctrl(devinfo, inst,
986 if (devinfo->ver >= 7) {
993 brw_inst_set_3src_a16_src_type(devinfo, inst, dest.type);
994 brw_inst_set_3src_a16_dst_type(devinfo, inst, dest.type);
1007 brw_inst_set_3src_a16_src1_type(devinfo, inst, 1);
1010 brw_inst_set_3src_a16_src2_type(devinfo, inst, 1);
1127 const struct intel_device_info *devinfo = p->devinfo;
1133 if (devinfo->verx10 == 70 &&
1252 const struct intel_device_info *devinfo = p->devinfo;
1260 (!align16 || devinfo->ver >= 8));
1266 if (devinfo->ver <= 7) {
1281 if (devinfo->ver >= 8) {
1284 assert(devinfo->ver == 7);
1289 if (devinfo->ver < 12)
1290 brw_inst_set_no_dd_clear(devinfo, inst, true);
1293 if (devinfo->ver < 12)
1294 brw_inst_set_no_dd_check(devinfo, inst, true);
1304 const struct intel_device_info *devinfo = p->devinfo;
1324 if (devinfo->ver >= 8) {
1327 assert(devinfo->ver == 7);
1343 brw_inst_set_cond_modifier(p->devinfo, insn, func);
1354 const struct intel_device_info *devinfo = p->devinfo;
1358 brw_inst_set_exec_size(devinfo, inst, BRW_EXECUTE_1);
1359 brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
1360 brw_inst_set_mask_control(devinfo, inst, BRW_MASK_DISABLE);
1361 brw_inst_set_pred_control(devinfo, inst, predicate_control);
1424 const struct intel_device_info *devinfo = p->devinfo;
1431 if (devinfo->ver < 6) {
1435 } else if (devinfo->ver == 6) {
1437 brw_inst_set_gfx6_jump_count(devinfo, insn, 0);
1440 } else if (devinfo->ver == 7) {
1444 brw_inst_set_jip(devinfo, insn, 0);
1445 brw_inst_set_uip(devinfo, insn, 0);
1448 if (devinfo->ver < 12)
1450 brw_inst_set_jip(devinfo, insn, 0);
1451 brw_inst_set_uip(devinfo, insn, 0);
1454 brw_inst_set_exec_size(devinfo, insn, execute_size);
1455 brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
1456 brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NORMAL);
1457 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_ENABLE);
1458 if (!p->single_program_flow && devinfo->ver < 6)
1459 brw_inst_set_thread_control(devinfo, insn, BRW_THREAD_SWITCH);
1473 const struct intel_device_info *devinfo = p->devinfo;
1479 brw_inst_set_exec_size(devinfo, insn, brw_get_default_exec_size(p));
1480 brw_inst_set_gfx6_jump_count(devinfo, insn, 0);
1484 assert(brw_inst_qtr_control(devinfo, insn) == BRW_COMPRESSION_NONE);
1485 assert(brw_inst_pred_control(devinfo, insn) == BRW_PREDICATE_NONE);
1486 brw_inst_set_cond_modifier(devinfo, insn, conditional);
1499 const struct intel_device_info *devinfo = p->devinfo;
1507 assert(brw_inst_exec_size(devinfo, if_inst) == BRW_EXECUTE_1);
1518 brw_inst_set_pred_inv(devinfo, if_inst, true);
1526 brw_inst_set_imm_ud(devinfo, if_inst, (else_inst - if_inst + 1) * 16);
1527 brw_inst_set_imm_ud(devinfo, else_inst, (next_inst - else_inst) * 16);
1529 brw_inst_set_imm_ud(devinfo, if_inst, (next_inst - if_inst) * 16);
1540 const struct intel_device_info *devinfo = p->devinfo;
1554 if (devinfo->ver < 6)
1561 unsigned br = brw_jump_scale(devinfo);
1564 brw_inst_set_exec_size(devinfo, endif_inst, brw_inst_exec_size(devinfo, if_inst));
1568 if (devinfo->ver < 6) {
1573 brw_inst_set_gfx4_jump_count(devinfo, if_inst,
1575 brw_inst_set_gfx4_pop_count(devinfo, if_inst, 0);
1576 } else if (devinfo->ver == 6) {
1578 brw_inst_set_gfx6_jump_count(devinfo, if_inst, br*(endif_inst - if_inst));
1580 brw_inst_set_uip(devinfo, if_inst, br * (endif_inst - if_inst));
1581 brw_inst_set_jip(devinfo, if_inst, br * (endif_inst - if_inst));
1584 brw_inst_set_exec_size(devinfo, else_inst, brw_inst_exec_size(devinfo, if_inst));
1587 if (devinfo->ver < 6) {
1588 brw_inst_set_gfx4_jump_count(devinfo, if_inst,
1590 brw_inst_set_gfx4_pop_count(devinfo, if_inst, 0);
1591 } else if (devinfo->ver == 6) {
1592 brw_inst_set_gfx6_jump_count(devinfo, if_inst,
1597 if (devinfo->ver < 6) {
1601 brw_inst_set_gfx4_jump_count(devinfo, else_inst,
1603 brw_inst_set_gfx4_pop_count(devinfo, else_inst, 1);
1604 } else if (devinfo->ver == 6) {
1606 brw_inst_set_gfx6_jump_count(devinfo, else_inst,
1610 brw_inst_set_jip(devinfo, if_inst, br * (else_inst - if_inst + 1));
1612 brw_inst_set_uip(devinfo, if_inst, br * (endif_inst - if_inst));
1613 brw_inst_set_jip(devinfo, else_inst, br * (endif_inst - else_inst));
1614 if (devinfo->ver >= 8) {
1618 brw_inst_set_uip(devinfo, else_inst, br * (endif_inst - else_inst));
1627 const struct intel_device_info *devinfo = p->devinfo;
1632 if (devinfo->ver < 6) {
1636 } else if (devinfo->ver == 6) {
1638 brw_inst_set_gfx6_jump_count(devinfo, insn, 0);
1641 } else if (devinfo->ver == 7) {
1645 brw_inst_set_jip(devinfo, insn, 0);
1646 brw_inst_set_uip(devinfo, insn, 0);
1649 if (devinfo->ver < 12)
1651 brw_inst_set_jip(devinfo, insn, 0);
1652 brw_inst_set_uip(devinfo, insn, 0);
1655 brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
1656 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_ENABLE);
1657 if (!p->single_program_flow && devinfo->ver < 6)
1658 brw_inst_set_thread_control(devinfo, insn, BRW_THREAD_SWITCH);
1666 const struct intel_device_info *devinfo = p->devinfo;
1685 if (devinfo->ver < 6 && p->single_program_flow)
1711 if (devinfo->ver < 6) {
1715 } else if (devinfo->ver == 6) {
1719 } else if (devinfo->ver == 7) {
1727 brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
1728 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_ENABLE);
1729 if (devinfo->ver < 6)
1730 brw_inst_set_thread_control(devinfo, insn, BRW_THREAD_SWITCH);
1733 if (devinfo->ver < 6) {
1734 brw_inst_set_gfx4_jump_count(devinfo, insn, 0);
1735 brw_inst_set_gfx4_pop_count(devinfo, insn, 1);
1736 } else if (devinfo->ver == 6) {
1737 brw_inst_set_gfx6_jump_count(devinfo, insn, 2);
1739 brw_inst_set_jip(devinfo, insn, 2);
1747 const struct intel_device_info *devinfo = p->devinfo;
1751 if (devinfo->ver >= 8) {
1754 } else if (devinfo->ver >= 6) {
1762 brw_inst_set_gfx4_pop_count(devinfo, insn,
1765 brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
1766 brw_inst_set_exec_size(devinfo, insn, brw_get_default_exec_size(p));
1774 const struct intel_device_info *devinfo = p->devinfo;
1779 if (devinfo->ver >= 8) {
1786 if (devinfo->ver < 6) {
1787 brw_inst_set_gfx4_pop_count(devinfo, insn,
1790 brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
1791 brw_inst_set_exec_size(devinfo, insn, brw_get_default_exec_size(p));
1798 const struct intel_device_info *devinfo = p->devinfo;
1803 if (devinfo->ver < 6) {
1812 } else if (devinfo->ver < 8) {
1815 } else if (devinfo->ver < 12) {
1819 brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
1820 brw_inst_set_exec_size(devinfo, insn, brw_get_default_exec_size(p));
1843 const struct intel_device_info *devinfo = p->devinfo;
1845 if (devinfo->ver >= 6 || p->single_program_flow) {
1859 brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
1860 brw_inst_set_exec_size(devinfo, insn, execute_size);
1861 brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE);
1877 const struct intel_device_info *devinfo = p->devinfo;
1880 unsigned br = brw_jump_scale(devinfo);
1882 assert(devinfo->ver < 6);
1890 brw_inst_gfx4_jump_count(devinfo, inst) == 0) {
1891 brw_inst_set_gfx4_jump_count(devinfo, inst, br*((while_inst - inst) + 1));
1893 brw_inst_gfx4_jump_count(devinfo, inst) == 0) {
1894 brw_inst_set_gfx4_jump_count(devinfo, inst, br * (while_inst - inst));
1902 const struct intel_device_info *devinfo = p->devinfo;
1904 unsigned br = brw_jump_scale(devinfo);
1906 if (devinfo->ver >= 6) {
1910 if (devinfo->ver >= 8) {
1912 if (devinfo->ver < 12)
1914 brw_inst_set_jip(devinfo, insn, br * (do_insn - insn));
1915 } else if (devinfo->ver == 7) {
1919 brw_inst_set_jip(devinfo, insn, br * (do_insn - insn));
1922 brw_inst_set_gfx6_jump_count(devinfo, insn, br * (do_insn - insn));
1927 brw_inst_set_exec_size(devinfo, insn, brw_get_default_exec_size(p));
1937 brw_inst_set_exec_size(devinfo, insn, BRW_EXECUTE_1);
1948 brw_inst_set_exec_size(devinfo, insn, brw_inst_exec_size(devinfo, do_insn));
1949 brw_inst_set_gfx4_jump_count(devinfo, insn, br * (do_insn - insn + 1));
1950 brw_inst_set_gfx4_pop_count(devinfo, insn, 0);
1955 brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
1966 const struct intel_device_info *devinfo = p->devinfo;
1970 if (devinfo->ver >= 5)
1974 assert(brw_inst_src1_reg_file(devinfo, jmp_insn) == BRW_IMMEDIATE_VALUE);
1976 brw_inst_set_gfx4_jump_count(devinfo, jmp_insn,
1990 const struct intel_device_info *devinfo = p->devinfo;
1993 brw_inst_set_cond_modifier(devinfo, insn, conditional);
2005 if (devinfo->ver == 7) {
2008 brw_inst_set_thread_control(devinfo, insn, BRW_THREAD_SWITCH);
2019 const struct intel_device_info *devinfo = p->devinfo;
2022 brw_inst_set_cond_modifier(devinfo, insn, conditional);
2035 if (devinfo->ver == 7) {
2038 brw_inst_set_thread_control(devinfo, insn, BRW_THREAD_SWITCH);
2056 const struct intel_device_info *devinfo = p->devinfo;
2065 assert(devinfo->ver < 6);
2070 brw_inst_set_pred_control(devinfo, insn, 0);
2071 brw_inst_set_base_mrf(devinfo, insn, msg_reg_nr);
2089 const struct intel_device_info *devinfo = p->devinfo;
2092 assert(devinfo->ver >= 6);
2095 (devinfo->ver >= 7 && dest.file == BRW_MESSAGE_REGISTER_FILE));
2098 if (devinfo->ver == 6) {
2109 (devinfo->ver >= 8 && src1.file == BRW_IMMEDIATE_VALUE));
2119 (src0.type == BRW_REGISTER_TYPE_HF && devinfo->ver >= 9));
2121 (src1.type == BRW_REGISTER_TYPE_HF && devinfo->ver >= 9));
2125 if (devinfo->ver == 6) {
2132 brw_inst_set_math_function(devinfo, insn, function);
2147 if (p->devinfo->ver >= 8)
2165 const struct intel_device_info *devinfo = p->devinfo;
2167 (devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE :
2168 devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
2173 if (devinfo->ver >= 6)
2214 brw_inst_set_sfid(devinfo, insn, target_cache);
2215 brw_inst_set_compression(devinfo, insn, false);
2217 if (brw_inst_exec_size(devinfo, insn) >= 16)
2220 assert(brw_inst_pred_control(devinfo, insn) == BRW_PREDICATE_NONE);
2221 if (devinfo->ver < 6)
2222 brw_inst_set_base_mrf(devinfo, insn, mrf.nr);
2234 if (devinfo->ver >= 6) {
2243 if (devinfo->ver >= 6) {
2249 if (devinfo->ver >= 6)
2255 brw_message_desc(devinfo, mlen, send_commit_msg, true) |
2256 brw_dp_write_desc(devinfo, brw_scratch_surface_idx(p),
2277 const struct intel_device_info *devinfo = p->devinfo;
2280 if (devinfo->ver >= 6)
2283 if (p->devinfo->ver >= 7) {
2299 (devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE :
2300 devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
2324 brw_inst_set_sfid(devinfo, insn, target_cache);
2325 assert(brw_inst_pred_control(devinfo, insn) == 0);
2326 brw_inst_set_compression(devinfo, insn, false);
2329 if (devinfo->ver >= 6) {
2333 brw_inst_set_base_mrf(devinfo, insn, mrf.nr);
2337 brw_message_desc(devinfo, 1, rlen, true) |
2338 brw_dp_read_desc(devinfo, brw_scratch_surface_idx(p),
2352 assert(brw_inst_pred_control(p->devinfo, insn) == BRW_PREDICATE_NONE);
2390 const struct intel_device_info *devinfo = p->devinfo;
2392 (devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_CONSTANT_CACHE :
2398 if (devinfo->ver >= 6)
2427 brw_inst_set_sfid(devinfo, insn, target_cache);
2433 if (devinfo->ver >= 6) {
2437 brw_inst_set_base_mrf(devinfo, insn, mrf.nr);
2441 brw_message_desc(devinfo, 1, DIV_ROUND_UP(exec_size, 8), true) |
2442 brw_dp_read_desc(devinfo, bind_table_index,
2462 const struct intel_device_info *devinfo = p->devinfo;
2464 (devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
2474 if (devinfo->ver >= 6) {
2479 brw_inst_set_sfid(devinfo, insn, target_cache);
2480 brw_inst_set_compression(devinfo, insn, false);
2482 if (devinfo->ver >= 6) {
2487 brw_inst_set_base_mrf(devinfo, insn, payload.nr);
2494 brw_message_desc(devinfo, msg_length, response_length,
2496 brw_fb_write_desc(devinfo, binding_table_index, msg_control,
2499 brw_inst_set_eot(devinfo, insn, eot);
2513 const struct intel_device_info *devinfo = p->devinfo;
2514 assert(devinfo->ver >= 9);
2517 brw_inst_set_sfid(devinfo, insn, GFX6_SFID_DATAPORT_RENDER_CACHE);
2522 brw_message_desc(devinfo, msg_length, response_length, true) |
2523 brw_fb_read_desc(devinfo, binding_table_index, 0 /* msg_control */,
2525 brw_inst_set_rt_slot_group(devinfo, insn, brw_get_default_group(p) / 16);
2548 const struct intel_device_info *devinfo = p->devinfo;
2555 brw_inst_set_sfid(devinfo, insn, BRW_SFID_SAMPLER);
2556 brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE); /* XXX */
2570 brw_inst_set_compression(devinfo, insn, false);
2572 if (devinfo->ver < 6)
2573 brw_inst_set_base_mrf(devinfo, insn, msg_reg_nr);
2578 brw_message_desc(devinfo, msg_length, response_length,
2580 brw_sampler_desc(devinfo, binding_table_index, sampler,
2600 const struct intel_device_info *devinfo = p->devinfo;
2607 assert(devinfo->verx10 >= 75);
2615 if (devinfo->verx10 <= 70) {
2647 const struct intel_device_info *devinfo = p->devinfo;
2652 if (devinfo->ver >= 7 && !(flags & BRW_URB_WRITE_USE_CHANNEL_MASKS)) {
2667 assert(msg_length < BRW_MAX_MRF(devinfo->ver));
2673 if (devinfo->ver < 6)
2674 brw_inst_set_base_mrf(devinfo, insn, msg_reg_nr);
2694 const struct intel_device_info *devinfo = p->devinfo;
2728 if (devinfo->ver >= 12)
2729 brw_inst_set_send_sel_reg32_desc(devinfo, send, true);
2735 brw_inst_set_sfid(devinfo, send, sfid);
2736 brw_inst_set_eot(devinfo, send, eot);
2751 const struct intel_device_info *devinfo = p->devinfo;
2784 (devinfo->ver >= 12 ||
2826 send = next_insn(p, devinfo->ver >= 12 ? BRW_OPCODE_SEND : BRW_OPCODE_SENDS);
2832 brw_inst_set_send_sel_reg32_desc(devinfo, send, 0);
2833 brw_inst_set_send_desc(devinfo, send, desc.ud);
2838 brw_inst_set_send_sel_reg32_desc(devinfo, send, 1);
2842 brw_inst_set_send_sel_reg32_ex_desc(devinfo, send, 0);
2843 brw_inst_set_sends_ex_desc(devinfo, send, ex_desc.ud);
2848 brw_inst_set_send_sel_reg32_ex_desc(devinfo, send, 1);
2849 brw_inst_set_send_ex_desc_ia_subreg_nr(devinfo, send, ex_desc.subnr >> 2);
2852 brw_inst_set_sfid(devinfo, send, sfid);
2853 brw_inst_set_eot(devinfo, send, eot);
2893 while_jumps_before_offset(const struct intel_device_info *devinfo,
2896 int scale = 16 / brw_jump_scale(devinfo);
2897 int jip = devinfo->ver == 6 ? brw_inst_gfx6_jump_count(devinfo, insn)
2898 : brw_inst_jip(devinfo, insn);
2909 const struct intel_device_info *devinfo = p->devinfo;
2913 for (offset = next_offset(devinfo, store, start_offset);
2915 offset = next_offset(devinfo, store, offset)) {
2931 if (!while_jumps_before_offset(devinfo, insn, offset, start_offset))
2954 const struct intel_device_info *devinfo = p->devinfo;
2958 assert(devinfo->ver >= 6);
2963 for (offset = next_offset(devinfo, store, start_offset);
2965 offset = next_offset(devinfo, store, offset)) {
2969 if (while_jumps_before_offset(devinfo, insn, offset, start_offset))
2983 const struct intel_device_info *devinfo = p->devinfo;
2985 int br = brw_jump_scale(devinfo);
2989 if (devinfo->ver < 6)
2994 assert(brw_inst_cmpt_control(devinfo, insn) == 0);
3000 brw_inst_set_jip(devinfo, insn, (block_end_offset - offset) / scale);
3002 brw_inst_set_uip(devinfo, insn,
3004 (devinfo->ver == 6 ? 16 : 0)) / scale);
3011 brw_inst_set_jip(devinfo, insn, (block_end_offset - offset) / scale);
3012 brw_inst_set_uip(devinfo, insn,
3015 assert(brw_inst_uip(devinfo, insn) != 0);
3016 assert(brw_inst_jip(devinfo, insn) != 0);
3024 if (devinfo->ver >= 7)
3025 brw_inst_set_jip(devinfo, insn, jump);
3027 brw_inst_set_gfx6_jump_count(devinfo, insn, jump);
3045 brw_inst_set_jip(devinfo, insn, brw_inst_uip(devinfo, insn));
3047 brw_inst_set_jip(devinfo, insn, (block_end_offset - offset) / scale);
3049 assert(brw_inst_uip(devinfo, insn) != 0);
3050 assert(brw_inst_jip(devinfo, insn) != 0);
3068 const struct intel_device_info *devinfo = p->devinfo;
3078 if (devinfo->ver < 6)
3079 brw_inst_set_base_mrf(devinfo, insn, msg_reg_nr);
3107 const struct intel_device_info *devinfo = p->devinfo;
3108 assert(devinfo->ver == 6);
3115 brw_inst_set_sfid(devinfo, insn, target_cache);
3119 brw_message_desc(devinfo, 1, send_commit_msg, true) |
3120 brw_dp_write_desc(devinfo, binding_table_index,
3148 const struct intel_device_info *devinfo = p->devinfo;
3149 const unsigned sfid = (devinfo->verx10 >= 75 ?
3154 const bool has_simd4x2 = devinfo->verx10 >= 75;
3160 brw_message_desc(devinfo, msg_length, response_length, header_present) |
3161 brw_dp_untyped_atomic_desc(devinfo, exec_size, atomic_op,
3183 const struct intel_device_info *devinfo = p->devinfo;
3184 const unsigned sfid = (devinfo->verx10 >= 75 ?
3192 brw_message_desc(devinfo, msg_length, response_length, false) |
3193 brw_dp_untyped_surface_rw_desc(devinfo, exec_size, num_channels, false);
3206 const struct intel_device_info *devinfo = p->devinfo;
3207 const unsigned sfid = (devinfo->verx10 >= 75 ?
3212 const bool has_simd4x2 = devinfo->verx10 >= 75;
3216 brw_message_desc(devinfo, msg_length, 0, header_present) |
3217 brw_dp_untyped_surface_rw_desc(devinfo, exec_size, num_channels, true);
3232 const struct intel_device_info *devinfo = p->devinfo;
3235 devinfo, 1, (commit_enable ? 1 : 0), true));
3237 brw_inst_set_sfid(devinfo, insn, sfid);
3241 brw_inst_set_dp_msg_type(devinfo, insn, GFX7_DATAPORT_RC_MEMORY_FENCE);
3244 brw_inst_set_dp_msg_type(devinfo, insn, GFX7_DATAPORT_DC_MEMORY_FENCE);
3251 brw_inst_set_dp_msg_control(devinfo, insn, 1 << 5);
3253 assert(devinfo->ver >= 11 || bti == 0);
3254 brw_inst_set_binding_table_index(devinfo, insn, bti);
3267 brw_inst_set_sfid(p->devinfo, insn, sfid);
3270 brw_set_desc(p, insn, brw_urb_fence_desc(p->devinfo) |
3271 brw_message_desc(p->devinfo, mlen, rlen, true));
3273 enum lsc_fence_scope scope = lsc_fence_msg_desc_scope(p->devinfo, desc);
3274 enum lsc_flush_type flush_type = lsc_fence_msg_desc_flush_type(p->devinfo, desc);
3292 if (intel_device_info_is_dg2(p->devinfo) &&
3298 brw_set_desc(p, insn, lsc_fence_msg_desc(p->devinfo, scope,
3300 brw_message_desc(p->devinfo, mlen, rlen, false));
3314 const struct intel_device_info *devinfo = p->devinfo;
3323 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
3324 brw_inst_set_exec_size(devinfo, insn, BRW_EXECUTE_1);
3329 if (devinfo->has_lsc)
3346 const struct intel_device_info *devinfo = p->devinfo;
3351 brw_message_desc(devinfo, msg_length, response_length, false) |
3352 brw_pixel_interp_desc(devinfo, mode, noperspective, coarse_pixel_rate,
3370 const struct intel_device_info *devinfo = p->devinfo;
3375 assert(devinfo->ver == 7);
3406 brw_inst_set_mask_control(devinfo, inst, BRW_MASK_ENABLE);
3407 brw_inst_set_group(devinfo, inst, lower_size * i + 8 * qtr_control);
3408 brw_inst_set_cond_modifier(devinfo, inst, BRW_CONDITIONAL_Z);
3409 brw_inst_set_exec_size(devinfo, inst, cvt(lower_size) - 1);
3410 brw_inst_set_flag_reg_nr(devinfo, inst, flag_subreg / 2);
3411 brw_inst_set_flag_subreg_nr(devinfo, inst, flag_subreg % 2);
3442 brw_inst_set_mask_control(devinfo, inst, BRW_MASK_ENABLE);
3454 const struct intel_device_info *devinfo = p->devinfo;
3477 if (type_sz(src.type) > 4 && !devinfo->has_64bit_float) {
3534 (devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo) ||
3535 !devinfo->has_64bit_float)) {
3566 brw_inst_set_pred_control(devinfo, inst, BRW_PREDICATE_NONE);
3567 brw_inst_set_cond_modifier(devinfo, inst, BRW_CONDITIONAL_NZ);
3568 brw_inst_set_flag_reg_nr(devinfo, inst, 1);
3574 brw_inst_set_pred_control(devinfo, inst, BRW_PREDICATE_NORMAL);
3575 brw_inst_set_flag_reg_nr(devinfo, inst, 1);
3589 const struct intel_device_info *devinfo = p->devinfo;
3592 assert(devinfo->ver >= 7);
3600 brw_set_desc(p, inst, brw_message_desc(devinfo, 1, 0, false));
3602 brw_inst_set_sfid(devinfo, inst, BRW_SFID_MESSAGE_GATEWAY);
3603 brw_inst_set_gateway_subfuncid(devinfo, inst,
3606 brw_inst_set_mask_control(devinfo, inst, BRW_MASK_DISABLE);
3617 const struct intel_device_info *devinfo = p->devinfo;
3627 brw_inst_set_exec_size(devinfo, insn, BRW_EXECUTE_1);
3628 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
3648 brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1);
3649 if (p->devinfo->ver < 12)
3650 brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH);
3655 brw_inst_set_exec_size(p->devinfo, inst_or, BRW_EXECUTE_1);
3656 if (p->devinfo->ver < 12)
3657 brw_inst_set_thread_control(p->devinfo, inst_or, BRW_THREAD_SWITCH);
3660 if (p->devinfo->ver >= 12)
3669 const struct intel_device_info *devinfo = isa->devinfo;
3673 assert(brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE);
3676 assert(brw_inst_cmpt_control(devinfo, inst) == 0);
3678 brw_inst_set_imm_ud(devinfo, inst, value);