Lines Matching refs:ctx
32 intel_batch_decode_ctx_init(struct intel_batch_decode_ctx *ctx,
44 memset(ctx, 0, sizeof(*ctx));
46 ctx->isa = isa;
47 ctx->devinfo = *devinfo;
48 ctx->get_bo = get_bo;
49 ctx->get_state_size = get_state_size;
50 ctx->user_data = user_data;
51 ctx->fp = fp;
52 ctx->flags = flags;
53 ctx->max_vbo_decoded_lines = -1; /* No limit! */
54 ctx->engine = I915_ENGINE_CLASS_RENDER;
57 ctx->spec = intel_spec_load(devinfo);
59 ctx->spec = intel_spec_load_from_path(devinfo, xml_path);
63 intel_batch_decode_ctx_finish(struct intel_batch_decode_ctx *ctx)
65 intel_spec_destroy(ctx->spec);
75 ctx_print_group(struct intel_batch_decode_ctx *ctx,
79 intel_print_group(ctx->fp, group, address, map, 0,
80 (ctx->flags & INTEL_BATCH_DECODE_IN_COLOR) != 0);
84 ctx_get_bo(struct intel_batch_decode_ctx *ctx, bool ppgtt, uint64_t addr)
86 if (intel_spec_get_gen(ctx->spec) >= intel_make_gen(8,0)) {
96 struct intel_batch_decode_bo bo = ctx->get_bo(ctx->user_data, ppgtt, addr);
98 if (intel_spec_get_gen(ctx->spec) >= intel_make_gen(8,0))
114 update_count(struct intel_batch_decode_ctx *ctx,
122 if (ctx->get_state_size)
123 size = ctx->get_state_size(ctx->user_data, address, base_address);
133 ctx_disassemble_program(struct intel_batch_decode_ctx *ctx,
136 uint64_t addr = ctx->instruction_base + ksp;
137 struct intel_batch_decode_bo bo = ctx_get_bo(ctx, true, addr);
141 fprintf(ctx->fp, "\nReferenced %s:\n", type);
142 intel_disassemble(ctx->isa, bo.map, 0, ctx->fp);
171 ctx_print_buffer(struct intel_batch_decode_ctx *ctx,
183 fprintf(ctx->fp, "\n");
192 fprintf(ctx->fp, column_count == 0 ? " " : " ");
194 if ((ctx->flags & INTEL_BATCH_DECODE_FLOATS) && probably_float(*dw))
195 fprintf(ctx->fp, " %8.2f", *(float *) dw);
197 fprintf(ctx->fp, " 0x%08x", *dw);
202 fprintf(ctx->fp, "\n");
206 intel_ctx_find_instruction(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
208 return intel_spec_find_instruction(ctx->spec, ctx->engine, p);
212 handle_state_base_address(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
214 struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
239 ctx->dynamic_base = dynamic_base;
242 ctx->surface_base = surface_base;
245 ctx->instruction_base = instruction_base;
249 handle_binding_table_pool_alloc(struct intel_batch_decode_ctx *ctx,
252 struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
268 if (bt_pool_enable || ctx->devinfo.verx10 >= 125) {
269 ctx->bt_pool_base = bt_pool_base;
271 ctx->bt_pool_base = 0;
276 dump_binding_table(struct intel_batch_decode_ctx *ctx,
280 intel_spec_find_struct(ctx->spec, "RENDER_SURFACE_STATE");
282 fprintf(ctx->fp, "did not find RENDER_SURFACE_STATE info\n");
290 if (ctx->devinfo.verx10 >= 125) {
293 } else if (ctx->use_256B_binding_tables) {
303 const uint64_t bt_pool_base = ctx->bt_pool_base ? ctx->bt_pool_base :
304 ctx->surface_base;
307 count = update_count(ctx, bt_pool_base + offset,
312 fprintf(ctx->fp, " invalid binding table pointer\n");
317 ctx_get_bo(ctx, true, bt_pool_base + offset);
320 fprintf(ctx->fp, " binding table unavailable\n");
329 uint64_t addr = ctx->surface_base + pointers[i];
330 struct intel_batch_decode_bo bo = ctx_get_bo(ctx, true, addr);
335 fprintf(ctx->fp, "pointer %u: 0x%08x <not valid>\n", i, pointers[i]);
339 fprintf(ctx->fp, "pointer %u: 0x%08x\n", i, pointers[i]);
340 ctx_print_group(ctx, strct, addr, bo.map + (addr - bo.addr));
345 dump_samplers(struct intel_batch_decode_ctx *ctx, uint32_t offset, int count)
347 struct intel_group *strct = intel_spec_find_struct(ctx->spec, "SAMPLER_STATE");
348 uint64_t state_addr = ctx->dynamic_base + offset;
352 struct intel_batch_decode_bo bo = ctx_get_bo(ctx, true, state_addr);
356 fprintf(ctx->fp, " samplers unavailable\n");
361 fprintf(ctx->fp, " invalid sampler state pointer\n");
368 fprintf(ctx->fp, " sampler state ends after bo ends\n");
374 fprintf(ctx->fp, "sampler state %d\n", i);
375 ctx_print_group(ctx, strct, state_addr, state_map);
382 handle_interface_descriptor_data(struct intel_batch_decode_ctx *ctx,
405 ctx_disassemble_program(ctx, ksp, "compute shader");
406 fprintf(ctx->fp, "\n");
409 dump_samplers(ctx, sampler_offset, sampler_count);
411 dump_binding_table(ctx, binding_table_offset, binding_entry_count);
415 handle_media_interface_descriptor_load(struct intel_batch_decode_ctx *ctx,
418 struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
420 intel_spec_find_struct(ctx->spec, "INTERFACE_DESCRIPTOR_DATA");
435 uint64_t desc_addr = ctx->dynamic_base + descriptor_offset;
436 struct intel_batch_decode_bo bo = ctx_get_bo(ctx, true, desc_addr);
440 fprintf(ctx->fp, " interface descriptors unavailable\n");
445 fprintf(ctx->fp, "descriptor %d: %08x\n", i, descriptor_offset);
447 ctx_print_group(ctx, desc, desc_addr, desc_map);
449 handle_interface_descriptor_data(ctx, desc, desc_map);
457 handle_compute_walker(struct intel_batch_decode_ctx *ctx,
460 struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
466 handle_interface_descriptor_data(ctx, iter.struct_desc,
473 handle_3dstate_vertex_buffers(struct intel_batch_decode_ctx *ctx,
476 struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
477 struct intel_group *vbs = intel_spec_find_struct(ctx->spec, "VERTEX_BUFFER_STATE");
499 vb = ctx_get_bo(ctx, true, vbs_iter.raw_value);
514 fprintf(ctx->fp, "vertex buffer %d, size %d\n", index, vb_size);
517 fprintf(ctx->fp, " buffer contents unavailable\n");
524 ctx_print_buffer(ctx, vb, vb_size, pitch, ctx->max_vbo_decoded_lines);
536 handle_3dstate_index_buffer(struct intel_batch_decode_ctx *ctx,
539 struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
551 ib = ctx_get_bo(ctx, true, iter.raw_value);
558 fprintf(ctx->fp, " buffer contents unavailable\n");
567 fprintf(ctx->fp, "%3d ", *(uint8_t *)m);
571 fprintf(ctx->fp, "%3d ", *(uint16_t *)m);
575 fprintf(ctx->fp, "%3d ", *(uint32_t *)m);
582 fprintf(ctx->fp, "...");
583 fprintf(ctx->fp, "\n");
587 decode_single_ksp(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
589 struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
592 bool is_simd8 = ctx->devinfo.ver >= 11; /* vertex shaders on Gfx8+ only */
623 ctx_disassemble_program(ctx, ksp, type);
624 fprintf(ctx->fp, "\n");
629 decode_mesh_task_ksp(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
631 struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
655 ctx_disassemble_program(ctx, ksp, type);
656 fprintf(ctx->fp, "\n");
661 decode_ps_kern(struct intel_batch_decode_ctx *ctx,
664 bool single_ksp = ctx->devinfo.ver == 4;
703 ctx_disassemble_program(ctx, ksp[0], "SIMD8 fragment shader");
705 ctx_disassemble_program(ctx, ksp[1], "SIMD16 fragment shader");
707 ctx_disassemble_program(ctx, ksp[2], "SIMD32 fragment shader");
710 fprintf(ctx->fp, "\n");
714 decode_ps_kernels(struct intel_batch_decode_ctx *ctx,
717 struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
718 decode_ps_kern(ctx, inst, p);
722 decode_3dstate_constant_all(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
725 intel_spec_find_instruction(ctx->spec, ctx->engine, p);
727 intel_spec_find_struct(ctx->spec, "3DSTATE_CONSTANT_ALL_DATA");
745 buffer[idx] = ctx_get_bo(ctx, true, iter.raw_value);
758 fprintf(ctx->fp, "constant buffer %d, size %u\n", i, size);
760 ctx_print_buffer(ctx, buffer[i], size, 0, -1);
765 decode_3dstate_constant(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
767 struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
769 intel_spec_find_struct(ctx->spec, "3DSTATE_CONSTANT_BODY");
797 struct intel_batch_decode_bo buffer = ctx_get_bo(ctx, true, read_addr[i]);
799 fprintf(ctx->fp, "constant buffer %d unavailable\n", i);
804 fprintf(ctx->fp, "constant buffer %d, size %u\n", i, size);
806 ctx_print_buffer(ctx, buffer, size, 0, -1);
812 decode_gfx4_constant_buffer(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
814 struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
832 struct intel_batch_decode_bo buffer = ctx_get_bo(ctx, true, read_addr);
834 fprintf(ctx->fp, "constant buffer unavailable\n");
838 fprintf(ctx->fp, "constant buffer size %u\n", size);
840 ctx_print_buffer(ctx, buffer, size, 0, -1);
845 decode_gfx4_3dstate_binding_table_pointers(struct intel_batch_decode_ctx *ctx,
848 fprintf(ctx->fp, "VS Binding Table:\n");
849 dump_binding_table(ctx, p[1], -1);
851 fprintf(ctx->fp, "GS Binding Table:\n");
852 dump_binding_table(ctx, p[2], -1);
854 if (ctx->devinfo.ver < 6) {
855 fprintf(ctx->fp, "CLIP Binding Table:\n");
856 dump_binding_table(ctx, p[3], -1);
857 fprintf(ctx->fp, "SF Binding Table:\n");
858 dump_binding_table(ctx, p[4], -1);
859 fprintf(ctx->fp, "PS Binding Table:\n");
860 dump_binding_table(ctx, p[5], -1);
862 fprintf(ctx->fp, "PS Binding Table:\n");
863 dump_binding_table(ctx, p[3], -1);
868 decode_3dstate_binding_table_pointers(struct intel_batch_decode_ctx *ctx,
871 dump_binding_table(ctx, p[1], -1);
875 decode_3dstate_sampler_state_pointers(struct intel_batch_decode_ctx *ctx,
878 dump_samplers(ctx, p[1], 1);
882 decode_3dstate_sampler_state_pointers_gfx6(struct intel_batch_decode_ctx *ctx,
885 dump_samplers(ctx, p[1], 1);
886 dump_samplers(ctx, p[2], 1);
887 dump_samplers(ctx, p[3], 1);
901 decode_dynamic_state(struct intel_batch_decode_ctx *ctx,
905 uint64_t state_addr = ctx->dynamic_base + state_offset;
906 struct intel_batch_decode_bo bo = ctx_get_bo(ctx, true, state_addr);
910 fprintf(ctx->fp, " dynamic %s state unavailable\n", struct_type);
914 struct intel_group *state = intel_spec_find_struct(ctx->spec, struct_type);
920 fprintf(ctx->fp, "%s\n", struct_type);
921 ctx_print_group(ctx, state, state_addr, state_map);
927 state = intel_spec_find_struct(ctx->spec, struct_type);
930 count = update_count(ctx, ctx->dynamic_base + state_offset,
931 ctx->dynamic_base, state->dw_length, count);
934 fprintf(ctx->fp, "%s %d\n", struct_type, i);
935 ctx_print_group(ctx, state, state_addr, state_map);
943 decode_dynamic_state_pointers(struct intel_batch_decode_ctx *ctx,
947 struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
959 decode_dynamic_state(ctx, struct_type, state_offset, count);
963 decode_3dstate_viewport_state_pointers(struct intel_batch_decode_ctx *ctx,
966 struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
980 decode_dynamic_state(ctx, "CLIP_VIEWPORT", state_offset, 1);
984 decode_dynamic_state(ctx, "SF_VIEWPORT", state_offset, 1);
988 decode_dynamic_state(ctx, "CC_VIEWPORT", state_offset, 1);
994 decode_3dstate_viewport_state_pointers_cc(struct intel_batch_decode_ctx *ctx,
997 decode_dynamic_state_pointers(ctx, "CC_VIEWPORT", p, 4);
1001 decode_3dstate_viewport_state_pointers_sf_clip(struct intel_batch_decode_ctx *ctx,
1004 decode_dynamic_state_pointers(ctx, "SF_CLIP_VIEWPORT", p, 4);
1008 decode_3dstate_blend_state_pointers(struct intel_batch_decode_ctx *ctx,
1011 decode_dynamic_state_pointers(ctx, "BLEND_STATE", p, 1);
1015 decode_3dstate_cc_state_pointers(struct intel_batch_decode_ctx *ctx,
1018 if (ctx->devinfo.ver != 6) {
1019 decode_dynamic_state_pointers(ctx, "COLOR_CALC_STATE", p, 1);
1023 struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
1038 decode_dynamic_state(ctx, "DEPTH_STENCIL_STATE", state_offset, 1);
1042 decode_dynamic_state(ctx, "BLEND_STATE", state_offset, 1);
1046 decode_dynamic_state(ctx, "COLOR_CALC_STATE", state_offset, 1);
1052 decode_3dstate_ds_state_pointers(struct intel_batch_decode_ctx *ctx,
1055 decode_dynamic_state_pointers(ctx, "DEPTH_STENCIL_STATE", p, 1);
1059 decode_3dstate_scissor_state_pointers(struct intel_batch_decode_ctx *ctx,
1062 decode_dynamic_state_pointers(ctx, "SCISSOR_RECT", p, 1);
1066 decode_3dstate_slice_table_state_pointers(struct intel_batch_decode_ctx *ctx,
1069 decode_dynamic_state_pointers(ctx, "SLICE_HASH_TABLE", p, 1);
1073 handle_gt_mode(struct intel_batch_decode_ctx *ctx,
1076 struct intel_group *reg = intel_spec_find_register(ctx->spec, reg_addr);
1095 ctx->use_256B_binding_tables = bt_alignment;
1100 void (*handler)(struct intel_batch_decode_ctx *ctx,
1107 decode_load_register_imm(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
1109 struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
1115 struct intel_group *reg = intel_spec_find_register(ctx->spec, p[i * 2 + 1]);
1117 fprintf(ctx->fp, "register %s (0x%x): 0x%x\n",
1119 ctx_print_group(ctx, reg, reg->register_offset, &p[2]);
1123 reg_handlers[i].handler(ctx, p[1], p[2]);
1130 decode_vs_state(struct intel_batch_decode_ctx *ctx, uint32_t offset)
1133 intel_spec_find_struct(ctx->spec, "VS_STATE");
1135 fprintf(ctx->fp, "did not find VS_STATE info\n");
1140 ctx_get_bo(ctx, true, offset);
1143 fprintf(ctx->fp, " vs state unavailable\n");
1147 ctx_print_group(ctx, strct, offset, bind_bo.map);
1161 ctx_disassemble_program(ctx, ksp, "vertex shader");
1162 fprintf(ctx->fp, "\n");
1167 decode_gs_state(struct intel_batch_decode_ctx *ctx, uint32_t offset)
1170 intel_spec_find_struct(ctx->spec, "GS_STATE");
1172 fprintf(ctx->fp, "did not find GS_STATE info\n");
1177 ctx_get_bo(ctx, true, offset);
1180 fprintf(ctx->fp, " gs state unavailable\n");
1184 ctx_print_group(ctx, strct, offset, bind_bo.map);
1188 decode_clip_state(struct intel_batch_decode_ctx *ctx, uint32_t offset)
1191 intel_spec_find_struct(ctx->spec, "CLIP_STATE");
1193 fprintf(ctx->fp, "did not find CLIP_STATE info\n");
1198 ctx_get_bo(ctx, true, offset);
1201 fprintf(ctx->fp, " clip state unavailable\n");
1205 ctx_print_group(ctx, strct, offset, bind_bo.map);
1208 intel_spec_find_struct(ctx->spec, "CLIP_VIEWPORT");
1210 fprintf(ctx->fp, "did not find CLIP_VIEWPORT info\n");
1215 ctx_get_bo(ctx, true, clip_vp_offset);
1217 fprintf(ctx->fp, " clip vp state unavailable\n");
1220 ctx_print_group(ctx, vp_strct, clip_vp_offset, vp_bo.map);
1224 decode_sf_state(struct intel_batch_decode_ctx *ctx, uint32_t offset)
1227 intel_spec_find_struct(ctx->spec, "SF_STATE");
1229 fprintf(ctx->fp, "did not find SF_STATE info\n");
1234 ctx_get_bo(ctx, true, offset);
1237 fprintf(ctx->fp, " sf state unavailable\n");
1241 ctx_print_group(ctx, strct, offset, bind_bo.map);
1244 intel_spec_find_struct(ctx->spec, "SF_VIEWPORT");
1246 fprintf(ctx->fp, "did not find SF_VIEWPORT info\n");
1252 ctx_get_bo(ctx, true, sf_vp_offset);
1254 fprintf(ctx->fp, " sf vp state unavailable\n");
1257 ctx_print_group(ctx, vp_strct, sf_vp_offset, vp_bo.map);
1261 decode_wm_state(struct intel_batch_decode_ctx *ctx, uint32_t offset)
1264 intel_spec_find_struct(ctx->spec, "WM_STATE");
1266 fprintf(ctx->fp, "did not find WM_STATE info\n");
1271 ctx_get_bo(ctx, true, offset);
1274 fprintf(ctx->fp, " wm state unavailable\n");
1278 ctx_print_group(ctx, strct, offset, bind_bo.map);
1280 decode_ps_kern(ctx, strct, bind_bo.map);
1284 decode_cc_state(struct intel_batch_decode_ctx *ctx, uint32_t offset)
1287 intel_spec_find_struct(ctx->spec, "COLOR_CALC_STATE");
1289 fprintf(ctx->fp, "did not find COLOR_CALC_STATE info\n");
1294 ctx_get_bo(ctx, true, offset);
1297 fprintf(ctx->fp, " cc state unavailable\n");
1301 ctx_print_group(ctx, strct, offset, bind_bo.map);
1304 intel_spec_find_struct(ctx->spec, "CC_VIEWPORT");
1306 fprintf(ctx->fp, "did not find CC_VIEWPORT info\n");
1311 ctx_get_bo(ctx, true, cc_vp_offset);
1313 fprintf(ctx->fp, " cc vp state unavailable\n");
1316 ctx_print_group(ctx, vp_strct, cc_vp_offset, vp_bo.map);
1319 decode_pipelined_pointers(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
1321 fprintf(ctx->fp, "VS State Table:\n");
1322 decode_vs_state(ctx, p[1]);
1324 fprintf(ctx->fp, "GS State Table:\n");
1325 decode_gs_state(ctx, p[2] & ~1);
1327 fprintf(ctx->fp, "Clip State Table:\n");
1328 decode_clip_state(ctx, p[3] & ~1);
1329 fprintf(ctx->fp, "SF State Table:\n");
1330 decode_sf_state(ctx, p[4]);
1331 fprintf(ctx->fp, "WM State Table:\n");
1332 decode_wm_state(ctx, p[5]);
1333 fprintf(ctx->fp, "CC State Table:\n");
1334 decode_cc_state(ctx, p[6]);
1338 decode_cps_pointers(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
1340 decode_dynamic_state_pointers(ctx, "CPS_STATE", p, 1);
1345 void (*decode)(struct intel_batch_decode_ctx *ctx, const uint32_t *p);
1397 intel_print_batch(struct intel_batch_decode_ctx *ctx,
1404 const char *reset_color = ctx->flags & INTEL_BATCH_DECODE_IN_COLOR ? NORMAL : "";
1406 if (ctx->n_batch_buffer_start >= 100) {
1407 fprintf(ctx->fp, "%s0x%08"PRIx64": Max batch buffer jumps exceeded%s\n",
1408 (ctx->flags & INTEL_BATCH_DECODE_IN_COLOR) ? RED_COLOR : "",
1409 (ctx->flags & INTEL_BATCH_DECODE_OFFSETS) ? batch_addr : 0,
1414 ctx->n_batch_buffer_start++;
1417 inst = intel_ctx_find_instruction(ctx, p);
1423 if (ctx->flags & INTEL_BATCH_DECODE_OFFSETS)
1429 fprintf(ctx->fp, "%s0x%08"PRIx64": unknown instruction %08x%s\n",
1430 (ctx->flags & INTEL_BATCH_DECODE_IN_COLOR) ? RED_COLOR : "",
1434 fprintf(ctx->fp, "%s0x%08"PRIx64": -- %08x%s\n",
1435 (ctx->flags & INTEL_BATCH_DECODE_IN_COLOR) ? RED_COLOR : "",
1444 if (ctx->flags & INTEL_BATCH_DECODE_IN_COLOR) {
1446 if (ctx->flags & INTEL_BATCH_DECODE_FULL) {
1460 fprintf(ctx->fp, "%s0x%08"PRIx64"%s: 0x%08x: %-80s%s\n", color, offset,
1461 ctx->acthd && offset == ctx->acthd ? " (ACTHD)" : "", p[0],
1464 if (ctx->flags & INTEL_BATCH_DECODE_FULL) {
1465 ctx_print_group(ctx, inst, offset, p);
1469 custom_decoders[i].decode(ctx, p);
1495 struct intel_batch_decode_bo next_batch = ctx_get_bo(ctx, ppgtt, next_batch_addr);
1498 fprintf(ctx->fp, "Secondary batch at 0x%08"PRIx64" unavailable\n",
1501 intel_print_batch(ctx, next_batch.map, next_batch.size,
1525 ctx->n_batch_buffer_start--;