Lines Matching defs:info
97 struct brw_blorp_surface_info *info,
103 memset(info, 0, sizeof(*info));
108 info->enabled = true;
113 info->surf = *surf->surf;
114 info->addr = surf->addr;
116 info->aux_usage = surf->aux_usage;
117 if (info->aux_usage != ISL_AUX_USAGE_NONE) {
118 info->aux_surf = *surf->aux_surf;
119 info->aux_addr = surf->aux_addr;
122 info->clear_color = surf->clear_color;
123 info->clear_color_addr = surf->clear_color_addr;
135 info->view = (struct isl_view) {
143 info->view.array_len = MAX2(info->surf.logical_level0_px.depth,
144 info->surf.logical_level0_px.array_len);
147 (info->surf.dim == ISL_SURF_DIM_3D ||
148 info->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY)) {
154 info->view.base_array_layer = 0;
155 info->z_offset = layer;
157 info->view.base_array_layer = layer;
159 assert(info->view.array_len >= info->view.base_array_layer);
160 info->view.array_len -= info->view.base_array_layer;
161 info->z_offset = 0;
167 if (is_dest && blorp->isl_dev->info->ver <= 6)
168 info->view.array_len = MIN2(info->view.array_len, 512);
172 assert(info->surf.dim == ISL_SURF_DIM_2D);
173 assert(info->surf.samples == 1);
174 assert(info->surf.levels == 1);
175 assert(info->surf.logical_level0_px.array_len == 1);
176 assert(info->aux_usage == ISL_AUX_USAGE_NONE);
178 info->tile_x_sa = surf->tile_x_sa;
179 info->tile_y_sa = surf->tile_y_sa;
186 info->surf.logical_level0_px.w += surf->tile_x_sa;
187 info->surf.logical_level0_px.h += surf->tile_y_sa;
188 info->surf.phys_level0_sa.w += surf->tile_x_sa;
189 info->surf.phys_level0_sa.h += surf->tile_y_sa;
246 if (nir->info.fs.uses_discard)
249 wm_key->input_slots_valid = nir->info.inputs_read | VARYING_BIT_POS;
278 vs_prog_data->inputs_read = nir->info.inputs_read;
282 nir->info.outputs_written,
283 nir->info.separate_shader,
411 const struct intel_device_info *devinfo = batch->blorp->isl_dev->info;