Lines Matching defs:gfx_pipeline
1333 struct pvr_graphics_pipeline *const gfx_pipeline)
1336 ARRAY_SIZE(gfx_pipeline->vertex_shader_state.pds_attrib_programs);
1341 &gfx_pipeline->fragment_shader_state.descriptor_state);
1346 &gfx_pipeline->vertex_shader_state.descriptor_state);
1350 &gfx_pipeline->vertex_shader_state.pds_attrib_programs[i];
1356 gfx_pipeline->fragment_shader_state.pds_fragment_program.pvr_bo);
1358 gfx_pipeline->fragment_shader_state.pds_coeff_program.pvr_bo);
1360 pvr_bo_free(device, gfx_pipeline->fragment_shader_state.bo);
1361 pvr_bo_free(device, gfx_pipeline->vertex_shader_state.bo);
1363 pvr_pipeline_finish(&gfx_pipeline->base);
1365 vk_free2(&device->vk.alloc, allocator, gfx_pipeline);
1369 pvr_vertex_state_init(struct pvr_graphics_pipeline *gfx_pipeline,
1374 &gfx_pipeline->vertex_shader_state;
1399 pvr_csb_pack (&gfx_pipeline->vertex_shader_state.varying[0],
1407 pvr_csb_pack (&gfx_pipeline->vertex_shader_state.varying[1],
1417 pvr_fragment_state_init(struct pvr_graphics_pipeline *gfx_pipeline,
1421 &gfx_pipeline->fragment_shader_state;
1446 struct pvr_graphics_pipeline *const gfx_pipeline)
1474 size_t stage_index = gfx_pipeline->stage_indices[stage];
1562 &gfx_pipeline->vertex_shader_state);
1564 pvr_vertex_state_init(gfx_pipeline,
1573 &gfx_pipeline->vertex_shader_state.bo);
1583 &gfx_pipeline->fragment_shader_state);
1585 pvr_fragment_state_init(gfx_pipeline,
1593 &gfx_pipeline->fragment_shader_state.bo);
1612 &gfx_pipeline->fragment_shader_state.pds_coeff_program);
1619 gfx_pipeline->fragment_shader_state.bo,
1623 &gfx_pipeline->fragment_shader_state.pds_fragment_program);
1633 &gfx_pipeline->vertex_shader_state.pds_attrib_programs);
1643 gfx_pipeline->base.layout,
1645 &gfx_pipeline->vertex_shader_state.descriptor_state);
1666 gfx_pipeline->base.layout,
1668 &gfx_pipeline->fragment_shader_state.descriptor_state);
1682 &gfx_pipeline->vertex_shader_state.descriptor_state);
1685 i < ARRAY_SIZE(gfx_pipeline->vertex_shader_state.pds_attrib_programs);
1688 &gfx_pipeline->vertex_shader_state.pds_attrib_programs[i];
1694 gfx_pipeline->fragment_shader_state.pds_fragment_program.pvr_bo);
1697 gfx_pipeline->fragment_shader_state.pds_coeff_program.pvr_bo);
1699 pvr_bo_free(device, gfx_pipeline->fragment_shader_state.bo);
1701 pvr_bo_free(device, gfx_pipeline->vertex_shader_state.bo);
1708 struct pvr_graphics_pipeline *gfx_pipeline,
1721 gfx_pipeline->depth_compare_op = depth_stencil_state->depthCompareOp;
1722 gfx_pipeline->depth_write_disable =
1725 gfx_pipeline->depth_compare_op = VK_COMPARE_OP_ALWAYS;
1726 gfx_pipeline->depth_write_disable = true;
1730 gfx_pipeline->stencil_front.compare_op = front->compareOp;
1731 gfx_pipeline->stencil_front.fail_op = front->failOp;
1732 gfx_pipeline->stencil_front.depth_fail_op = front->depthFailOp;
1733 gfx_pipeline->stencil_front.pass_op = front->passOp;
1735 gfx_pipeline->stencil_back.compare_op = back->compareOp;
1736 gfx_pipeline->stencil_back.fail_op = back->failOp;
1737 gfx_pipeline->stencil_back.depth_fail_op = back->depthFailOp;
1738 gfx_pipeline->stencil_back.pass_op = back->passOp;
1740 gfx_pipeline->stencil_front.compare_op = VK_COMPARE_OP_ALWAYS;
1741 gfx_pipeline->stencil_front.fail_op = VK_STENCIL_OP_KEEP;
1742 gfx_pipeline->stencil_front.depth_fail_op = VK_STENCIL_OP_KEEP;
1743 gfx_pipeline->stencil_front.pass_op = VK_STENCIL_OP_KEEP;
1745 gfx_pipeline->stencil_back = gfx_pipeline->stencil_front;
1750 struct pvr_graphics_pipeline *gfx_pipeline,
1758 &gfx_pipeline->dynamic_state;
1841 struct pvr_graphics_pipeline *gfx_pipeline)
1860 pvr_pipeline_init(device, PVR_PIPELINE_TYPE_GRAPHICS, &gfx_pipeline->base);
1865 gfx_pipeline->raster_state.discard_enable = raster_discard_enabled;
1866 gfx_pipeline->raster_state.cull_mode =
1868 gfx_pipeline->raster_state.front_face =
1870 gfx_pipeline->raster_state.depth_bias_enable =
1872 gfx_pipeline->raster_state.depth_clamp_enable =
1877 pvr_graphics_pipeline_init_depth_and_stencil_state(gfx_pipeline, dss_info);
1878 pvr_graphics_pipeline_init_dynamic_state(gfx_pipeline,
1886 gfx_pipeline->input_asm_state.topology =
1888 gfx_pipeline->input_asm_state.primitive_restart =
1892 memset(gfx_pipeline->stage_indices, ~0, sizeof(gfx_pipeline->stage_indices));
1912 gfx_pipeline->stage_indices[gl_stage] = i;
1919 gfx_pipeline->base.layout =
1923 gfx_pipeline->rasterization_samples = ms_info->rasterizationSamples;
1924 gfx_pipeline->sample_mask =
1927 gfx_pipeline->rasterization_samples = VK_SAMPLE_COUNT_1_BIT;
1928 gfx_pipeline->sample_mask = 0xFFFFFFFF;
1936 gfx_pipeline);
1938 pvr_pipeline_finish(&gfx_pipeline->base);
1953 struct pvr_graphics_pipeline *gfx_pipeline;
1956 gfx_pipeline = vk_zalloc2(&device->vk.alloc,
1958 sizeof(*gfx_pipeline),
1961 if (!gfx_pipeline)
1969 gfx_pipeline);
1971 vk_free2(&device->vk.alloc, allocator, gfx_pipeline);
1975 *pipeline_out = pvr_pipeline_to_handle(&gfx_pipeline->base);
2024 struct pvr_graphics_pipeline *const gfx_pipeline =
2027 pvr_graphics_pipeline_destroy(device, pAllocator, gfx_pipeline);