Lines Matching defs:value
362 /* Note that the unit of the return value depends on the GPU. For cores with the
770 pvr_csb_pack (&isp_mtile_size, CR_ISP_MTILE_SIZE, value) {
771 value.x = mtile_info->mtile_x1;
772 value.y = mtile_info->mtile_y1;
776 value.x <<= 1;
779 value.y <<= 1;
782 value.x <<= 1;
785 value.y <<= 1;
788 value.y <<= 1;
790 assert(!"Unsupported ISP samples per pixel value");
831 pvr_csb_pack (&multisamplectl, CR_PPP_MULTISAMPLECTL, value) {
834 value.msaa_x7 = sample_positions[idx].x[7];
835 value.msaa_x6 = sample_positions[idx].x[6];
836 value.msaa_x5 = sample_positions[idx].x[5];
837 value.msaa_x4 = sample_positions[idx].x[4];
840 value.msaa_y7 = 16U - sample_positions[idx].y[7];
841 value.msaa_y6 = 16U - sample_positions[idx].y[6];
842 value.msaa_y5 = 16U - sample_positions[idx].y[5];
843 value.msaa_y4 = 16U - sample_positions[idx].y[4];
845 value.msaa_y7 = sample_positions[idx].y[7];
846 value.msaa_y6 = sample_positions[idx].y[6];
847 value.msaa_y5 = sample_positions[idx].y[5];
848 value.msaa_y4 = sample_positions[idx].y[4];
853 value.msaa_x3 = sample_positions[idx].x[3];
854 value.msaa_x2 = sample_positions[idx].x[2];
857 value.msaa_y3 = 16U - sample_positions[idx].y[3];
858 value.msaa_y2 = 16U - sample_positions[idx].y[2];
860 value.msaa_y3 = sample_positions[idx].y[3];
861 value.msaa_y2 = sample_positions[idx].y[2];
866 value.msaa_x1 = sample_positions[idx].x[1];
869 value.msaa_y1 = 16U - sample_positions[idx].y[1];
871 value.msaa_y1 = sample_positions[idx].y[1];
876 value.msaa_x0 = sample_positions[idx].x[0];
879 value.msaa_y0 = 16U - sample_positions[idx].y[0];
881 value.msaa_y0 = sample_positions[idx].y[0];
901 pvr_csb_pack (&te_aa, CR_TE_AA, value) {
904 value.y = true;
906 value.x = true;
909 value.x2 = true;
911 value.y = true;
913 value.x = true;
916 value.x2 = true;
918 value.y2 = true;
920 value.y = true;
922 assert(!"Unsupported ISP samples per pixel value");
945 float value;
948 value =
950 create_info->isp_merge_lower_x = fui(value);
952 value =
954 create_info->isp_merge_upper_x = fui(value);
958 value =
960 create_info->isp_merge_lower_y = fui(value);
962 value =
964 create_info->isp_merge_upper_y = fui(value);
967 value = ((float)rt_dataset->width * ROGUE_ISP_MERGE_SCALE_FACTOR) /
970 create_info->isp_merge_scale_x = fui(value);
972 value = ((float)rt_dataset->height * ROGUE_ISP_MERGE_SCALE_FACTOR) /
975 create_info->isp_merge_scale_y = fui(value);
989 pvr_csb_pack (&create_info->ppp_screen, CR_PPP_SCREEN, value) {
990 value.pixxmax = rt_dataset->width - 1;
991 value.pixymax = rt_dataset->height - 1;
998 pvr_csb_pack (&create_info->te_mtile1, CR_TE_MTILE1, value) {
999 value.x1 = mtile_info->mtile_x1;
1001 value.x2 = mtile_info->mtile_x2;
1002 value.x3 = mtile_info->mtile_x3;
1006 pvr_csb_pack (&create_info->te_mtile2, CR_TE_MTILE2, value) {
1007 value.y1 = mtile_info->mtile_y1;
1009 value.y2 = mtile_info->mtile_y2;
1010 value.y3 = mtile_info->mtile_y3;
1014 pvr_csb_pack (&create_info->te_screen, CR_TE_SCREEN, value) {
1015 value.xmax = mtile_info->x_tile_max;
1016 value.ymax = mtile_info->y_tile_max;
1172 * ignore the value anyway.
1175 pvr_csb_pack (&state->regs.pds_ctrl, CR_PDS_CTRL, value) {
1176 value.max_num_vdm_tasks = rogue_get_max_num_vdm_pds_tasks(dev_info);
1182 pvr_csb_pack (&state->regs.ppp_ctrl, CR_PPP_CTRL, value) {
1183 value.wclampen = true;
1184 value.fixed_point_format = 1;
1187 pvr_csb_pack (&state->regs.te_psg, CR_TE_PSG, value) {
1188 value.completeonterminate = job->geometry_terminate;
1190 value.region_stride = job->rt_dataset->rgn_headers_stride /
1193 value.forcenewstate = PVR_HAS_QUIRK(dev_info, 52942);
1199 pvr_csb_pack (&state->regs.tpu, CR_TPU, value) {
1200 value.tag_cem_4k_face_packing = true;
1205 value) {
1206 value.border_colour_table_address = job->border_colour_table_addr;
1211 value) {
1212 value.addr = job->ctrl_stream_addr;
1221 value) {
1225 value.usc_common_size =
1318 pvr_csb_pack (&state->regs.isp_ctl, CR_ISP_CTL, value) {
1319 value.sample_pos = true;
1324 value.process_empty_tiles = job->process_empty_tiles;
1329 * of the value.
1333 pvr_csb_pack (&state->regs.isp_aa, CR_ISP_AA, value) {
1334 value.mode = isp_aa_mode;
1340 pvr_csb_pack (&state->regs.tpu, CR_TPU, value) {
1341 value.tag_cem_4k_face_packing = true;
1359 pvr_csb_pack (&state->regs.isp_bgobjvals, CR_ISP_BGOBJVALS, value) {
1360 value.enablebgtag = job->enable_bg_tag;
1362 value.mask = true;
1367 value.stencil = 0xFF;
1370 pvr_csb_pack (&state->regs.isp_bgobjdepth, CR_ISP_BGOBJDEPTH, value) {
1375 value.value = fui(job->depth_clear_value);
1381 pvr_csb_pack (&state->regs.isp_zlsctl, CR_ISP_ZLSCTL, value) {
1391 &value.zlsextent_x_z,
1392 &value.zlsextent_y_z);
1393 value.zlsextent_x_z -= 1;
1394 value.zlsextent_y_z -= 1;
1397 value.loadtwiddled = true;
1398 value.storetwiddled = true;
1406 value.zloadformat = PVRX(CR_ZLOADFORMAT_TYPE_F32Z);
1407 value.zstoreformat = PVRX(CR_ZSTOREFORMAT_TYPE_F32Z);
1411 pvr_csb_pack (&state->regs.isp_zls_pixels, CR_ISP_ZLS_PIXELS, value) {
1412 value.x = job->depth_stride - 1;
1413 value.y = job->depth_height - 1;
1419 pvr_csb_pack (&state->regs.isp_zload_store_base, CR_ISP_ZLOAD_BASE, value) {
1420 value.addr = job->depth_addr;
1425 value) {
1426 value.addr = job->stencil_addr;
1428 /* FIXME: May need to set value.enable to true. */
1433 value) {
1434 value.border_colour_table_address = job->border_colour_table_addr;
1439 pvr_csb_pack (&state->regs.isp_dbias_base, CR_ISP_DBIAS_BASE, value) {
1440 value.addr = job->depth_bias_table_addr;
1443 pvr_csb_pack (&state->regs.isp_scissor_base, CR_ISP_SCISSOR_BASE, value) {
1444 value.addr = job->scissor_table_addr;
1449 value) {
1450 value.const_size =
1453 value.temp_stride = 0;
1454 value.usc_sr_size =
1461 value) {
1462 value.addr = PVR_DEV_ADDR(job->pds_pixel_event_data_offset);