Lines Matching refs:PVRX
138 PVRX(TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE),
141 PVRX(TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE),
211 PVRX(TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE),
214 PVRX(TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE),
298 PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE),
316 PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE) / 4U;
352 PVRX(VDMCTRL_PDS_STATE1_PDS_DATA_ADDR_ALIGNMENT),
355 PVRX(VDMCTRL_PDS_STATE2_PDS_CODE_ADDR_ALIGNMENT),
375 PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE) / 4U;
427 STATIC_ASSERT(PVRX(CR_CDM_CONTEXT_PDS0_DATA_ADDR_ALIGNMENT) ==
428 PVRX(CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_ALIGNMENT));
430 STATIC_ASSERT(PVRX(CR_CDM_CONTEXT_PDS0_CODE_ADDR_ALIGNMENT) ==
431 PVRX(CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_ALIGNMENT));
437 PVRX(CR_CDM_CONTEXT_PDS0_DATA_ADDR_ALIGNMENT),
440 PVRX(CR_CDM_CONTEXT_PDS0_CODE_ADDR_ALIGNMENT),
455 PVRX(LLS_USC_SHARED_REGS_BUFFER_SIZE) +
470 DIV_ROUND_UP(64, PVRX(VDMCTRL_PDS_STATE0_USC_UNIFIED_SIZE_UNIT_SIZE));
707 enum PVRX(VDMCTRL_USC_TARGET) usc_target,
716 state.dm_target = PVRX(VDMCTRL_DM_TARGET_VDM);
722 assert(pds_data_size % PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE) ==
725 pds_data_size / PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE);
730 state.sd_type = PVRX(VDMCTRL_SD_TYPE_PDS);
731 state.sd_next_type = PVRX(VDMCTRL_SD_TYPE_PDS);
747 PVRX(TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE) ==
750 pds_data_size / PVRX(TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE);
785 PVRX(VDMCTRL_USC_TARGET_ANY),
810 PVRX(VDMCTRL_USC_TARGET_ALL),
866 PVRX(CR_VDM_CALL_STACK_POINTER_ADDR_ALIGNMENT),
927 PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE) / 4U;
931 uint32_t staging_buffer[PVRX(PDS_TASK_PROGRAM_SIZE) >> 2U];
967 PVRX(CR_CDM_TERMINATE_PDS_DATA_ADDR_ALIGNMENT),
970 PVRX(CR_CDM_TERMINATE_PDS_CODE_ADDR_ALIGNMENT),
1018 PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE) ==
1021 PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE);
1054 PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE) ==
1057 PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE);