Lines Matching refs:state
132 cmd_buffer->state.render_pass_info.attachments);
134 cmd_buffer->state.render_pass_info.clear_values);
177 cmd_buffer->state.status = VK_SUCCESS;
223 struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
245 for (uint32_t i = 0; i < ARRAY_SIZE(state->barriers_needed); i++)
246 state->barriers_needed[i] |= barriers;
300 cmd_buffer->state.render_pass_info.framebuffer;
535 &cmd_buffer->state.render_pass_info;
580 &cmd_buffer->state.render_pass_info;
880 &cmd_buffer->state.render_pass_info;
1058 job->max_shared_registers = cmd_buffer->state.max_shared_regs;
1098 cmd_buffer->state.max_shared_regs);
1100 cmd_buffer->state.max_shared_regs = 0U;
1332 struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
1334 &state->current_sub_cmd->compute.pds_sw_barrier_requires_clearing;
1419 struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
1420 struct pvr_sub_cmd *sub_cmd = state->current_sub_cmd;
1438 state->status = result;
1451 state->status = result;
1457 state->status = result;
1463 state->status = result;
1471 state->status = result;
1485 state->status = result;
1503 state->current_sub_cmd = NULL;
1508 static void pvr_reset_graphics_dirty_state(struct pvr_cmd_buffer_state *state,
1514 * It's the driver's responsibility to ensure that the state of the
1516 * phase. This is required to prevent stale state from a previous
1518 * following fields in PPP State Header, and their corresponding state
1547 state->emit_state_bits = 0;
1549 state->emit_state.stream_out = true;
1550 state->emit_state.ppp_control = true;
1551 state->emit_state.varying_word2 = true;
1552 state->emit_state.varying_word1 = true;
1553 state->emit_state.varying_word0 = true;
1554 state->emit_state.output_selects = true;
1555 state->emit_state.wclamp = true;
1556 state->emit_state.viewport = true;
1557 state->emit_state.region_clip = true;
1558 state->emit_state.pds_fragment_stateptr0 = true;
1559 state->emit_state.isp_fb = true;
1560 state->emit_state.isp = true;
1562 state->emit_state.ppp_control = true;
1563 state->emit_state.varying_word1 = true;
1564 state->emit_state.varying_word0 = true;
1565 state->emit_state.output_selects = true;
1566 state->emit_state.viewport = true;
1567 state->emit_state.region_clip = true;
1568 state->emit_state.pds_fragment_stateptr0 = true;
1569 state->emit_state.isp_fb = true;
1570 state->emit_state.isp = true;
1573 memset(&state->ppp_state, 0U, sizeof(state->ppp_state));
1575 state->dirty.vertex_bindings = true;
1576 state->dirty.gfx_pipeline_binding = true;
1577 state->dirty.viewport = true;
1583 struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
1589 if (state->status != VK_SUCCESS)
1590 return state->status;
1594 if (state->current_sub_cmd) {
1595 if (state->current_sub_cmd->type == type) {
1611 state->status = vk_error(cmd_buffer, VK_ERROR_OUT_OF_HOST_MEMORY);
1612 return state->status;
1628 sub_cmd->gfx.hw_render_idx = state->render_pass_info.current_hw_subpass;
1629 sub_cmd->gfx.framebuffer = state->render_pass_info.framebuffer;
1632 pvr_reset_graphics_dirty_state(state, true);
1654 state->current_sub_cmd = sub_cmd;
1677 cmd_buffer->state.status = result;
1699 cmd_buffer->state.compute_pipeline = compute_pipeline;
1700 cmd_buffer->state.dirty.compute_pipeline_binding = true;
1708 &cmd_buffer->state.dynamic.common;
1711 struct pvr_cmd_buffer_state *const cmd_buffer_state = &cmd_buffer->state;
1872 struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
1887 if (state->dynamic.common.viewport.count < total_count)
1888 state->dynamic.common.viewport.count = total_count;
1890 memcpy(&state->dynamic.common.viewport.viewports[firstViewport],
1894 state->dirty.viewport = true;
1904 struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
1911 if (state->dynamic.common.scissor.count < total_count)
1912 state->dynamic.common.scissor.count = total_count;
1914 memcpy(&state->dynamic.common.scissor.scissors[firstScissor],
1918 state->dirty.scissor = true;
1924 struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
1926 state->dynamic.common.line_width = lineWidth;
1927 state->dirty.line_width = true;
1936 struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
1938 state->dynamic.common.depth_bias.constant_factor = depthBiasConstantFactor;
1939 state->dynamic.common.depth_bias.clamp = depthBiasClamp;
1940 state->dynamic.common.depth_bias.slope_factor = depthBiasSlopeFactor;
1941 state->dirty.depth_bias = true;
1948 struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
1950 STATIC_ASSERT(ARRAY_SIZE(state->dynamic.common.blend_constants) == 4);
1951 memcpy(state->dynamic.common.blend_constants,
1953 sizeof(state->dynamic.common.blend_constants));
1955 state->dirty.blend_constants = true;
1970 struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
1973 state->dynamic.common.compare_mask.front = compareMask;
1976 state->dynamic.common.compare_mask.back = compareMask;
1978 state->dirty.compare_mask = true;
1986 struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
1989 state->dynamic.common.write_mask.front = writeMask;
1992 state->dynamic.common.write_mask.back = writeMask;
1994 state->dirty.write_mask = true;
2002 struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
2005 state->dynamic.common.reference.front = reference;
2008 state->dynamic.common.reference.back = reference;
2010 state->dirty.reference = true;
2040 descriptor_state = &cmd_buffer->state.gfx_desc_state;
2041 cmd_buffer->state.dirty.gfx_desc_dirty = true;
2043 descriptor_state = &cmd_buffer->state.compute_desc_state;
2044 cmd_buffer->state.dirty.compute_desc_dirty = true;
2065 struct pvr_vertex_binding *const vb = cmd_buffer->state.vertex_bindings;
2081 cmd_buffer->state.dirty.vertex_bindings = true;
2091 struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
2099 state->index_buffer_binding.buffer = index_buffer;
2100 state->index_buffer_binding.offset = offset;
2101 state->index_buffer_binding.type = indexType;
2102 state->dirty.index_buffer_binding = true;
2117 struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
2123 memcpy(&state->push_constants.data[offset], pValues, size);
2125 state->push_constants.dirty_stages |= stageFlags;
2133 struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
2134 struct pvr_render_pass_info *info = &state->render_pass_info;
2139 vk_free(&cmd_buffer->vk.pool->alloc, state->render_pass_info.attachments);
2153 state->status = vk_error(cmd_buffer, VK_ERROR_OUT_OF_HOST_MEMORY);
2154 return state->status;
2216 struct pvr_render_pass_info *info = &cmd_buffer->state.render_pass_info;
2282 struct pvr_render_pass_info *info = &cmd_buffer->state.render_pass_info;
2335 static void pvr_stash_depth_format(struct pvr_cmd_buffer_state *state,
2338 const struct pvr_render_pass *pass = state->render_pass_info.pass;
2343 struct pvr_image_view **iviews = state->render_pass_info.attachments;
2345 state->depth_format = iviews[hw_render->ds_surface_id]->vk.format;
2380 struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
2383 vk_free(&cmd_buffer->vk.pool->alloc, state->render_pass_info.clear_values);
2387 sizeof(*state->render_pass_info.clear_values);
2389 state->render_pass_info.clear_values =
2394 if (!state->render_pass_info.clear_values) {
2395 state->status = vk_error(cmd_buffer, VK_ERROR_OUT_OF_HOST_MEMORY);
2396 return state->status;
2399 memcpy(state->render_pass_info.clear_values,
2403 state->render_pass_info.clear_values = NULL;
2406 state->render_pass_info.clear_value_count =
2422 struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
2427 assert(!state->render_pass_info.pass);
2432 state->render_pass_info.pass = pass;
2433 state->render_pass_info.framebuffer = framebuffer;
2434 state->render_pass_info.subpass_idx = 0;
2435 state->render_pass_info.render_area = pRenderPassBeginInfo->renderArea;
2436 state->render_pass_info.current_hw_subpass = 0;
2437 state->render_pass_info.pipeline_bind_point =
2439 state->render_pass_info.userpass_spawn = pass->subpasses[0].userpass_spawn;
2440 state->dirty.userpass_spawn = true;
2446 state->status =
2448 if (state->status != VK_SUCCESS)
2470 pvr_stash_depth_format(&cmd_buffer->state,
2471 &cmd_buffer->state.current_sub_cmd->gfx);
2474 state->dynamic.scissor_accum_state = PVR_SCISSOR_ACCUM_CHECK_FOR_CLEAR;
2475 state->dynamic.scissor_accum_bounds.offset.x = 0;
2476 state->dynamic.scissor_accum_bounds.offset.y = 0;
2477 state->dynamic.scissor_accum_bounds.extent.width = 0;
2478 state->dynamic.scissor_accum_bounds.extent.height = 0;
2480 state->dynamic.scissor_accum_state = PVR_SCISSOR_ACCUM_DISABLED;
2500 cmd_buffer->state.status = VK_SUCCESS;
2509 struct pvr_cmd_buffer_state *state;
2515 state = &cmd_buffer->state;
2538 state->render_pass_info.pass = pass;
2539 state->render_pass_info.framebuffer =
2541 state->render_pass_info.subpass_idx = inheritance_info->subpass;
2542 state->render_pass_info.userpass_spawn =
2551 memset(state->barriers_needed,
2553 sizeof(*state->barriers_needed) * ARRAY_SIZE(state->barriers_needed));
2570 sub_cmd = &cmd_buffer->state.current_sub_cmd->transfer;
2604 struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
2605 const struct pvr_pds_info *const pds_info = state->pds_shader.info;
2667 state->draw_state.base_instance,
2680 &state->vertex_bindings[attribute->binding_index];
2700 state->pds_vertex_attrib_offset =
2745 desc_state = &cmd_buffer->state.gfx_desc_state;
2749 desc_state = &cmd_buffer->state.compute_desc_state;
2938 struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
2940 const struct pvr_compute_pipeline *pipeline = state->compute_pipeline;
2942 pipeline->state.shader.const_shared_reg_count;
2968 if (pipeline->state.descriptor.pds_info.code_size_in_dwords) {
2970 pipeline->state.descriptor.pds_info.data_size_in_dwords;
2972 info.pds_data_offset = state->pds_compute_descriptor_data_offset;
2978 assert(pipeline->state.descriptor.pds_code.code_size);
2979 info.pds_code_offset = pipeline->state.descriptor.pds_code.code_offset;
3038 struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
3040 const struct pvr_compute_pipeline *pipeline = state->compute_pipeline;
3042 &pipeline->state.primary_program_info;
3054 .pds_data_offset = pipeline->state.primary_program.data_offset,
3055 .pds_code_offset = pipeline->state.primary_program.code_offset,
3060 DIV_ROUND_UP(pipeline->state.shader.input_register_count << 2U,
3072 uint32_t work_size = pipeline->state.shader.work_size;
3080 coeff_regs = pipeline->state.shader.coefficient_register_count;
3090 coeff_regs += pipeline->state.shader.const_shared_reg_count;
3112 struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
3114 state->compute_pipeline;
3129 sub_cmd = &state->current_sub_cmd->compute;
3131 sub_cmd->uses_atomic_ops |= compute_pipeline->state.shader.uses_atomic_ops;
3132 sub_cmd->uses_barrier |= compute_pipeline->state.shader.uses_barrier;
3135 /* TODO: Add a dirty push constants mask in the cmd_buffer state and
3143 if (compute_pipeline->state.shader.uses_num_workgroups) {
3156 &compute_pipeline->state.descriptor,
3158 &state->pds_compute_descriptor_data_offset);
3163 state->dirty.compute_desc_dirty) ||
3164 state->dirty.compute_pipeline_binding || push_descriptors_dirty) {
3168 &compute_pipeline->state.descriptor,
3170 &state->pds_compute_descriptor_data_offset);
3188 pvr_update_draw_state(struct pvr_cmd_buffer_state *const state,
3191 /* We don't have a state to tell us that base_instance is being used so it
3199 * The only draw call state that doesn't really matter is the start vertex
3200 * as that is handled properly in the VDM state in all cases.
3202 if ((state->draw_state.draw_indexed != draw_state->draw_indexed) ||
3203 (state->draw_state.draw_indirect != draw_state->draw_indirect) ||
3204 (state->draw_state.base_instance == 0 &&
3206 state->dirty.draw_variant = true;
3207 } else if (state->draw_state.base_instance != draw_state->base_instance) {
3208 state->dirty.draw_base_instance = true;
3211 state->draw_state = *draw_state;
3239 const struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
3242 &state->gfx_pipeline->vertex_shader_state.descriptor_state;
3244 &state->gfx_pipeline->vertex_shader_state.stage_state;
3275 struct pvr_emit_state *const emit_state = &cmd_buffer->state.emit_state;
3277 cmd_buffer->state.gfx_pipeline;
3278 struct pvr_ppp_state *const ppp_state = &cmd_buffer->state.ppp_state;
3283 /* TODO: Handle vertex and fragment shader state flags. */
3285 pvr_csb_pack (&output_selects, TA_OUTPUT_SEL, state) {
3289 state.rhw_pres = true;
3290 state.vtxsize = DIV_ROUND_UP(vertex_state->vertex_output_size, 4U);
3291 state.psprite_size_pres = (topology == VK_PRIMITIVE_TOPOLOGY_POINT_LIST);
3314 struct pvr_emit_state *const emit_state = &cmd_buffer->state.emit_state;
3316 cmd_buffer->state.gfx_pipeline;
3317 struct pvr_ppp_state *const ppp_state = &cmd_buffer->state.ppp_state;
3319 &cmd_buffer->state.dynamic.common;
3321 &cmd_buffer->state.render_pass_info;
3456 /* Single face, using front state. */
3458 /* Single face, using back state. */
3585 struct pvr_emit_state *const emit_state = &cmd_buffer->state.emit_state;
3586 struct pvr_ppp_state *const ppp_state = &cmd_buffer->state.ppp_state;
3588 &cmd_buffer->state.dynamic.common;
3696 struct pvr_emit_state *const emit_state = &cmd_buffer->state.emit_state;
3697 struct pvr_ppp_state *const ppp_state = &cmd_buffer->state.ppp_state;
3728 struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
3730 &state->gfx_pipeline->fragment_shader_state.descriptor_state;
3732 &state->gfx_pipeline->fragment_shader_state.pds_coeff_program;
3734 &state->gfx_pipeline->fragment_shader_state.stage_state;
3736 struct pvr_emit_state *const emit_state = &state->emit_state;
3737 struct pvr_ppp_state *const ppp_state = &state->ppp_state;
3775 &state->gfx_pipeline->fragment_shader_state.pds_fragment_program;
3812 state->emit_state.pds_fragment_stateptr1 = true;
3826 base.addr = PVR_DEV_ADDR(state->pds_fragment_descriptor_data_offset);
3835 struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
3836 struct pvr_emit_state *const emit_state = &state->emit_state;
3837 struct pvr_ppp_state *const ppp_state = &state->ppp_state;
3839 if (ppp_state->viewport_count != state->dynamic.common.viewport.count) {
3840 ppp_state->viewport_count = state->dynamic.common.viewport.count;
3844 if (state->gfx_pipeline->raster_state.discard_enable) {
3855 VkViewport *viewport = &state->dynamic.common.viewport.viewports[i];
3883 struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
3884 const struct pvr_graphics_pipeline *const gfx_pipeline = state->gfx_pipeline;
3885 struct pvr_emit_state *const emit_state = &state->emit_state;
3886 struct pvr_ppp_state *const ppp_state = &state->ppp_state;
3958 struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
3959 struct pvr_emit_state *const emit_state = &state->emit_state;
3960 struct pvr_ppp_state *const ppp_state = &state->ppp_state;
3980 /* Set ISP state. */
4004 * If deferred_secondary is true then we do a separate state update
4024 /* PDS state. */
4039 /* We don't use the pds_fragment_stateptr2 (texture state programs)
4041 * because the hardware runs the texture state program only when the
4042 * pds_texture state field of PDS_SIZEINFO1 is non-zero.
4138 /* Write the VDM state update into the VDM control stream. */
4153 state->emit_state_bits = 0;
4162 struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
4163 const struct pvr_graphics_pipeline *const gfx_pipeline = state->gfx_pipeline;
4164 const bool dirty_stencil = state->dirty.compare_mask ||
4165 state->dirty.write_mask || state->dirty.reference;
4168 if (!(dirty_stencil || state->dirty.depth_bias ||
4169 state->dirty.fragment_descriptors || state->dirty.line_width ||
4170 state->dirty.gfx_pipeline_binding || state->dirty.scissor ||
4171 state->dirty.userpass_spawn || state->dirty.viewport ||
4172 state->emit_state_bits)) {
4176 if (state->dirty.gfx_pipeline_binding) {
4182 } else if (dirty_stencil || state->dirty.line_width ||
4183 state->dirty.userpass_spawn) {
4188 state->dirty.fragment_descriptors &&
4195 if (state->dirty.viewport)
4282 /* FIXME: Assume all state is dirty for the moment. */
4289 const struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
4290 const struct pvr_graphics_pipeline *const gfx_pipeline = state->gfx_pipeline;
4298 /* CAM Calculations and HW state take vertex size aligned to DWORDS. */
4336 state->dirty.gfx_pipeline_binding || state->dirty.vertex_bindings ||
4337 state->dirty.draw_base_instance || state->dirty.draw_variant;
4343 state0.vs_other_present = state->dirty.gfx_pipeline_binding ||
4344 state->dirty.draw_variant;
4359 switch (state->index_buffer_binding.type) {
4381 PVR_DEV_ADDR(state->pds_vertex_attrib_offset);
4391 PVR_DEV_ADDR(state->pds_shader.code_offset);
4405 DIV_ROUND_UP(state->pds_shader.info->temps_required << 2,
4408 DIV_ROUND_UP(state->pds_shader.info->data_size_in_dwords << 2,
4416 struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
4417 const struct pvr_graphics_pipeline *const gfx_pipeline = state->gfx_pipeline;
4430 sub_cmd = &state->current_sub_cmd->gfx;
4472 fstencil_writemask_zero = (state->dynamic.common.write_mask.front == 0);
4473 bstencil_writemask_zero = (state->dynamic.common.write_mask.back == 0);
4491 if (state->dirty.vertex_bindings || state->dirty.gfx_pipeline_binding ||
4492 state->dirty.draw_variant || state->dirty.draw_base_instance) {
4496 if (state->draw_state.draw_indirect)
4498 else if (state->draw_state.base_instance)
4505 state->pds_shader.info = &program->info;
4506 state->pds_shader.code_offset = program->program.code_offset;
4508 state->max_shared_regs =
4509 MAX2(state->max_shared_regs, pvr_calc_shared_regs_count(gfx_pipeline));
4518 state->dirty.vertex_descriptors = push_descriptors_dirty ||
4519 state->dirty.gfx_pipeline_binding;
4520 state->dirty.fragment_descriptors = state->dirty.vertex_descriptors;
4522 if (state->dirty.fragment_descriptors) {
4526 &state->gfx_pipeline->fragment_shader_state.descriptor_state,
4528 &state->pds_fragment_descriptor_data_offset);
4535 if (state->dirty.vertex_descriptors) {
4541 &state->gfx_pipeline->vertex_shader_state.descriptor_state,
4557 state->dirty.gfx_desc_dirty = false;
4558 state->dirty.blend_constants = false;
4559 state->dirty.compare_mask = false;
4560 state->dirty.depth_bias = false;
4561 state->dirty.draw_base_instance = false;
4562 state->dirty.draw_variant = false;
4563 state->dirty.fragment_descriptors = false;
4564 state->dirty.line_width = false;
4565 state->dirty.gfx_pipeline_binding = false;
4566 state->dirty.reference = false;
4567 state->dirty.scissor = false;
4568 state->dirty.userpass_spawn = false;
4569 state->dirty.vertex_bindings = false;
4570 state->dirty.viewport = false;
4571 state->dirty.write_mask = false;
4615 struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
4624 cmd_buffer->state.gfx_pipeline->vertex_shader_state.stage_state
4629 /* First instance is not handled in the VDM state, it's implemented as
4640 if (state->draw_state.draw_indexed) {
4641 struct pvr_buffer *buffer = state->index_buffer_binding.buffer;
4643 switch (state->index_buffer_binding.type) {
4661 state->index_buffer_binding.offset + first_index * index_stride);
4707 struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
4717 pvr_update_draw_state(state, &draw_state);
4725 &state->current_sub_cmd->gfx,
4726 state->gfx_pipeline->input_asm_state.topology,
4742 struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
4752 pvr_update_draw_state(state, &draw_state);
4760 &state->current_sub_cmd->gfx,
4761 state->gfx_pipeline->input_asm_state.topology,
4798 struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
4805 assert(state->render_pass_info.pass);
4806 assert(state->render_pass_info.framebuffer);
4821 attachments = state->render_pass_info.attachments;
4822 clear_values = state->render_pass_info.clear_values;
4824 memset(&state->render_pass_info, 0, sizeof(state->render_pass_info));
4826 state->render_pass_info.attachments = attachments;
4827 state->render_pass_info.clear_values = clear_values;
4851 struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
4853 state->render_pass_info.pass;
4889 required_stage_mask |= state->barriers_needed[stage];
4897 state->barriers_needed[stage] &= ~src_stage_mask;
4915 struct pvr_sub_cmd *const current_sub_cmd = state->current_sub_cmd;
4993 struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
4998 * CommandBuffer must be in the recording state.
5002 if (state->status != VK_SUCCESS)
5003 return state->status;