Lines Matching refs:tx
527 #define IS_VS (tx->processor == PIPE_SHADER_VERTEX)
528 #define IS_PS (tx->processor == PIPE_SHADER_FRAGMENT)
530 #define FAILURE_VOID(cond) if ((cond)) {tx->failure=1;return;}
548 nine_record_outputs(struct shader_translator *tx, BYTE Usage, BYTE UsageIndex,
551 tx->output_info[tx->num_outputs].output_semantic = Usage;
552 tx->output_info[tx->num_outputs].output_semantic_index = UsageIndex;
553 tx->output_info[tx->num_outputs].mask = mask;
554 tx->output_info[tx->num_outputs].output_index = output_index;
555 tx->num_outputs++;
558 static struct ureg_src nine_float_constant_src(struct shader_translator *tx, int idx)
562 if (tx->slot_map)
563 idx = tx->slot_map[idx];
569 if (tx->info->swvp_on && idx >= 4096) {
578 if (!tx->info->swvp_on)
579 tx->slots_used[idx] = TRUE;
580 if (tx->info->const_float_slots < (idx + 1))
581 tx->info->const_float_slots = idx + 1;
582 if (tx->num_slots < (idx + 1))
583 tx->num_slots = idx + 1;
588 static struct ureg_src nine_integer_constant_src(struct shader_translator *tx, int idx)
592 if (tx->info->swvp_on) {
596 unsigned slot_idx = tx->info->const_i_base + idx;
597 if (tx->slot_map)
598 slot_idx = tx->slot_map[slot_idx];
601 tx->slots_used[slot_idx] = TRUE;
602 tx->info->int_slots_used[idx] = TRUE;
603 if (tx->num_slots < (slot_idx + 1))
604 tx->num_slots = slot_idx + 1;
607 if (tx->info->const_int_slots < (idx + 1))
608 tx->info->const_int_slots = idx + 1;
613 static struct ureg_src nine_boolean_constant_src(struct shader_translator *tx, int idx)
620 if (tx->info->swvp_on) {
624 unsigned slot_idx = tx->info->const_b_base + r;
625 if (tx->slot_map)
626 slot_idx = tx->slot_map[slot_idx];
629 tx->slots_used[slot_idx] = TRUE;
630 tx->info->bool_slots_used[idx] = TRUE;
631 if (tx->num_slots < (slot_idx + 1))
632 tx->num_slots = slot_idx + 1;
636 if (tx->info->const_bool_slots < (idx + 1))
637 tx->info->const_bool_slots = idx + 1;
643 tx_lconstf(struct shader_translator *tx, struct ureg_src *src, INT index)
647 if (index < 0 || index >= tx->num_constf_allowed) {
648 tx->failure = TRUE;
651 for (i = 0; i < tx->num_lconstf; ++i) {
652 if (tx->lconstf[i].idx == index) {
653 *src = tx->lconstf[i].reg;
660 tx_lconsti(struct shader_translator *tx, struct ureg_src *src, INT index)
664 if (index < 0 || index >= tx->num_consti_allowed) {
665 tx->failure = TRUE;
668 for (i = 0; i < tx->num_lconsti; ++i) {
669 if (tx->lconsti[i].idx == index) {
670 *src = tx->lconsti[i].reg;
677 tx_lconstb(struct shader_translator *tx, struct ureg_src *src, INT index)
681 if (index < 0 || index >= tx->num_constb_allowed) {
682 tx->failure = TRUE;
685 for (i = 0; i < tx->num_lconstb; ++i) {
686 if (tx->lconstb[i].idx == index) {
687 *src = tx->lconstb[i].reg;
695 tx_set_lconstf(struct shader_translator *tx, INT index, float f[4])
699 FAILURE_VOID(index < 0 || index >= tx->num_constf_allowed)
701 for (n = 0; n < tx->num_lconstf; ++n)
702 if (tx->lconstf[n].idx == index)
704 if (n == tx->num_lconstf) {
706 tx->lconstf = REALLOC(tx->lconstf,
707 (n + 0) * sizeof(tx->lconstf[0]),
708 (n + 8) * sizeof(tx->lconstf[0]));
709 assert(tx->lconstf);
711 tx->num_lconstf++;
713 tx->lconstf[n].idx = index;
714 tx->lconstf[n].reg = ureg_imm4f(tx->ureg, f[0], f[1], f[2], f[3]);
716 memcpy(tx->lconstf[n].f, f, sizeof(tx->lconstf[n].f));
719 tx_set_lconsti(struct shader_translator *tx, INT index, int i[4])
723 FAILURE_VOID(index < 0 || index >= tx->num_consti_allowed)
725 for (n = 0; n < tx->num_lconsti; ++n)
726 if (tx->lconsti[n].idx == index)
728 if (n == tx->num_lconsti) {
730 tx->lconsti = REALLOC(tx->lconsti,
731 (n + 0) * sizeof(tx->lconsti[0]),
732 (n + 8) * sizeof(tx->lconsti[0]));
733 assert(tx->lconsti);
735 tx->num_lconsti++;
738 tx->lconsti[n].idx = index;
739 tx->lconsti[n].reg = tx->native_integers ?
740 ureg_imm4i(tx->ureg, i[0], i[1], i[2], i[3]) :
741 ureg_imm4f(tx->ureg, i[0], i[1], i[2], i[3]);
744 tx_set_lconstb(struct shader_translator *tx, INT index, BOOL b)
748 FAILURE_VOID(index < 0 || index >= tx->num_constb_allowed)
750 for (n = 0; n < tx->num_lconstb; ++n)
751 if (tx->lconstb[n].idx == index)
753 if (n == tx->num_lconstb) {
755 tx->lconstb = REALLOC(tx->lconstb,
756 (n + 0) * sizeof(tx->lconstb[0]),
757 (n + 8) * sizeof(tx->lconstb[0]));
758 assert(tx->lconstb);
760 tx->num_lconstb++;
763 tx->lconstb[n].idx = index;
764 tx->lconstb[n].reg = tx->native_integers ?
765 ureg_imm1u(tx->ureg, b ? 0xffffffff : 0) :
766 ureg_imm1f(tx->ureg, b ? 1.0f : 0.0f);
770 tx_scratch(struct shader_translator *tx)
772 if (tx->num_scratch >= ARRAY_SIZE(tx->regs.t)) {
773 tx->failure = TRUE;
774 return tx->regs.t[0];
776 if (ureg_dst_is_undef(tx->regs.t[tx->num_scratch]))
777 tx->regs.t[tx->num_scratch] = ureg_DECL_local_temporary(tx->ureg);
778 return tx->regs.t[tx->num_scratch++];
782 tx_scratch_scalar(struct shader_translator *tx)
784 return ureg_writemask(tx_scratch(tx), TGSI_WRITEMASK_X);
798 tx_temp_alloc(struct shader_translator *tx, INT idx)
801 if (idx >= tx->num_temp) {
802 unsigned k = tx->num_temp;
804 tx->regs.r = REALLOC(tx->regs.r,
805 k * sizeof(tx->regs.r[0]),
806 n * sizeof(tx->regs.r[0]));
808 tx->regs.r[k] = ureg_dst_undef();
809 tx->num_temp = n;
811 if (ureg_dst_is_undef(tx->regs.r[idx]))
812 tx->regs.r[idx] = ureg_DECL_temporary(tx->ureg);
816 tx_addr_alloc(struct shader_translator *tx, INT idx)
819 if (ureg_dst_is_undef(tx->regs.address))
820 tx->regs.address = ureg_DECL_address(tx->ureg);
821 if (ureg_dst_is_undef(tx->regs.a0))
822 tx->regs.a0 = ureg_DECL_temporary(tx->ureg);
826 TEX_if_fetch4(struct shader_translator *tx, struct ureg_dst dst,
831 struct ureg_src src_tg4[3] = {src0, ureg_imm1f(tx->ureg, 0.f), src1};
833 if (!(tx->info->fetch4 & (1 << idx)))
838 tmp = tx_scratch(tx);
839 ureg_tex_insn(tx->ureg, TGSI_OPCODE_TG4, &tmp, 1, target, TGSI_RETURN_TYPE_FLOAT,
841 ureg_MOV(tx->ureg, dst, ureg_swizzle(ureg_src(tmp), NINE_SWIZZLE4(Z, X, Y, W)));
854 apply_ps1x_projection(struct shader_translator *tx, struct ureg_dst dst,
858 unsigned dim = 1 + ((tx->info->projected >> (2 * idx)) & 3);
862 ureg_MOV(tx->ureg, dst, src);
864 tmp = tx_scratch_scalar(tx);
865 ureg_RCP(tx->ureg, tmp, ureg_scalar(src, dim-1));
866 ureg_MUL(tx->ureg, dst, tx_src_scalar(tmp), src);
871 TEX_with_ps1x_projection(struct shader_translator *tx, struct ureg_dst dst,
875 unsigned dim = 1 + ((tx->info->projected >> (2 * idx)) & 3);
877 boolean shadow = !!(tx->info->sampler_mask_shadow & (1 << idx));
884 ureg_TEX(tx->ureg, dst, target, src0, src1);
886 ureg_TXP(tx->ureg, dst, target, src0, src1);
888 tmp = tx_scratch(tx);
889 apply_ps1x_projection(tx, tmp, src0, idx);
890 ureg_TEX(tx->ureg, dst, target, ureg_src(tmp), src1);
895 tx_texcoord_alloc(struct shader_translator *tx, INT idx)
898 assert(idx >= 0 && idx < ARRAY_SIZE(tx->regs.vT));
899 if (ureg_src_is_undef(tx->regs.vT[idx]))
900 tx->regs.vT[idx] = ureg_DECL_fs_input(tx->ureg, tx->texcoord_sn, idx,
905 tx_bgnloop(struct shader_translator *tx)
907 tx->loop_depth++;
908 if (tx->loop_depth_max < tx->loop_depth)
909 tx->loop_depth_max = tx->loop_depth;
910 assert(tx->loop_depth < NINE_MAX_LOOP_DEPTH);
911 return &tx->loop_labels[tx->loop_depth - 1];
915 tx_endloop(struct shader_translator *tx)
917 assert(tx->loop_depth);
918 tx->loop_depth--;
919 ureg_fixup_label(tx->ureg, tx->loop_labels[tx->loop_depth],
920 ureg_get_instruction_number(tx->ureg));
921 return &tx->loop_labels[tx->loop_depth];
925 tx_get_loopctr(struct shader_translator *tx, boolean loop_or_rep)
927 const unsigned l = tx->loop_depth - 1;
929 if (!tx->loop_depth)
935 if (ureg_dst_is_undef(tx->regs.rL[l])) {
937 tx->regs.rL[l] = ureg_DECL_local_temporary(tx->ureg);
938 tx->loop_or_rep[l] = loop_or_rep;
941 assert(tx->loop_or_rep[l] == loop_or_rep);
943 return tx->regs.rL[l];
947 tx_get_loopal(struct shader_translator *tx)
949 int loop_level = tx->loop_depth - 1;
953 if (tx->loop_or_rep[loop_level])
955 return ureg_scalar(ureg_src(tx->regs.rL[loop_level]), TGSI_SWIZZLE_Y);
964 tx_cond(struct shader_translator *tx)
966 assert(tx->cond_depth <= NINE_MAX_COND_DEPTH);
967 tx->cond_depth++;
968 return &tx->cond_labels[tx->cond_depth - 1];
972 tx_elsecond(struct shader_translator *tx)
974 assert(tx->cond_depth);
975 return &tx->cond_labels[tx->cond_depth - 1];
979 tx_endcond(struct shader_translator *tx)
981 assert(tx->cond_depth);
982 tx->cond_depth--;
983 ureg_fixup_label(tx->ureg, tx->cond_labels[tx->cond_depth],
984 ureg_get_instruction_number(tx->ureg));
994 nine_get_position_input(struct shader_translator *tx)
996 struct ureg_program *ureg = tx->ureg;
998 if (tx->wpos_is_sysval)
1006 tx_src_param(struct shader_translator *tx, const struct sm1_src_param *param)
1008 struct ureg_program *ureg = tx->ureg;
1013 (param->file == D3DSPR_INPUT && tx->version.major == 3));
1018 tx_temp_alloc(tx, param->idx);
1019 src = ureg_src(tx->regs.r[param->idx]);
1027 assert(!ureg_dst_is_undef(tx->regs.a0));
1030 if (tx->version.major < 2 && tx->version.minor < 2)
1031 ureg_ARL(ureg, tx->regs.address, ureg_src(tx->regs.a0));
1033 ureg_ARR(ureg, tx->regs.address, ureg_src(tx->regs.a0));
1034 src = ureg_src(tx->regs.address);
1036 if (tx->version.major < 2 && tx->version.minor < 4) {
1038 src = ureg_src(tx->regs.tS[param->idx]);
1040 tx_texcoord_alloc(tx, param->idx);
1041 src = tx->regs.vT[param->idx];
1049 if (tx->version.major < 3) {
1053 tx->info->force_color_in_centroid ?
1068 if (ureg_src_is_undef(tx->regs.v_consecutive)) {
1070 tx->regs.v_consecutive = ureg_src(ureg_DECL_array_temporary(ureg, 10, 0));
1072 if (!ureg_src_is_undef(tx->regs.v[i]))
1073 ureg_MOV(ureg, ureg_dst_array_offset(ureg_dst(tx->regs.v_consecutive), i), tx->regs.v[i]);
1075 ureg_MOV(ureg, ureg_dst_array_offset(ureg_dst(tx->regs.v_consecutive), i), ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
1078 src = ureg_src_array_offset(tx->regs.v_consecutive, param->idx);
1080 assert(param->idx < ARRAY_SIZE(tx->regs.v));
1081 src = tx->regs.v[param->idx];
1086 src = ureg_src_indirect(src, tx_src_param(tx, param->rel));
1089 if (ureg_dst_is_undef(tx->regs.predicate)) {
1091 tx->failure = TRUE;
1092 tx->regs.predicate = ureg_DECL_temporary(tx->ureg);
1094 src = ureg_src(tx->regs.predicate);
1102 if (param->rel || !tx_lconstf(tx, &src, param->idx)) {
1103 src = nine_float_constant_src(tx, param->idx);
1105 tx->indirect_const_access = TRUE;
1106 src = ureg_src_indirect(src, tx_src_param(tx, param->rel));
1109 if (!IS_VS && tx->version.major < 2) {
1111 tmp = tx_scratch(tx);
1126 if (!tx_lconsti(tx, &src, param->idx))
1127 src = nine_integer_constant_src(tx, param->idx);
1130 if (!tx_lconstb(tx, &src, param->idx))
1131 src = nine_boolean_constant_src(tx, param->idx);
1134 if (ureg_dst_is_undef(tx->regs.address))
1135 tx->regs.address = ureg_DECL_address(ureg);
1136 if (!tx->native_integers)
1137 ureg_ARR(ureg, tx->regs.address, tx_get_loopal(tx));
1139 ureg_UARL(ureg, tx->regs.address, tx_get_loopal(tx));
1140 src = ureg_src(tx->regs.address);
1145 if (ureg_src_is_undef(tx->regs.vPos))
1146 tx->regs.vPos = nine_get_position_input(tx);
1147 if (tx->shift_wpos) {
1149 struct ureg_dst wpos = tx_scratch(tx);
1150 ureg_ADD(ureg, wpos, tx->regs.vPos,
1154 src = tx->regs.vPos;
1158 if (ureg_src_is_undef(tx->regs.vFace)) {
1159 if (tx->face_is_sysval_integer) {
1161 tx->regs.vFace =
1165 ureg_UCMP(ureg, tmp, ureg_scalar(tx->regs.vFace, TGSI_SWIZZLE_X),
1167 tx->regs.vFace = ureg_src(tmp);
1169 tx->regs.vFace = ureg_DECL_fs_input(ureg,
1173 tx->regs.vFace = ureg_scalar(tx->regs.vFace, TGSI_SWIZZLE_X);
1175 src = tx->regs.vFace;
1190 tmp = tx_scratch(tx);
1197 tmp = tx_scratch(tx);
1225 tmp = tx_scratch(tx);
1230 tmp = tx_scratch(tx);
1235 if (tx->native_integers && param->file == D3DSPR_CONSTBOOL) {
1236 tmp = tx_scratch(tx);
1241 tmp = tx_scratch(tx);
1247 tmp = tx_scratch(tx);
1256 tmp = tx_scratch(tx);
1261 tmp = tx_scratch(tx);
1266 tmp = tx_scratch(tx);
1271 tmp = tx_scratch(tx);
1284 _tx_dst_param(struct shader_translator *tx, const struct sm1_dst_param *param)
1292 tx_temp_alloc(tx, param->idx);
1293 dst = tx->regs.r[param->idx];
1298 if (tx->version.major < 2 && !IS_VS) {
1299 if (ureg_dst_is_undef(tx->regs.tS[param->idx]))
1300 tx->regs.tS[param->idx] = ureg_DECL_temporary(tx->ureg);
1301 dst = tx->regs.tS[param->idx];
1303 if (!IS_VS && tx->insn.opcode == D3DSIO_TEXKILL) { /* maybe others, too */
1304 tx_texcoord_alloc(tx, param->idx);
1305 dst = ureg_dst(tx->regs.vT[param->idx]);
1307 tx_addr_alloc(tx, param->idx);
1308 dst = tx->regs.a0;
1315 if (ureg_dst_is_undef(tx->regs.oPos))
1316 tx->regs.oPos =
1317 ureg_DECL_output(tx->ureg, TGSI_SEMANTIC_POSITION, 0);
1318 dst = tx->regs.oPos;
1321 if (ureg_dst_is_undef(tx->regs.oFog))
1322 tx->regs.oFog =
1323 ureg_saturate(ureg_DECL_output(tx->ureg, TGSI_SEMANTIC_GENERIC, 16));
1324 dst = tx->regs.oFog;
1327 if (ureg_dst_is_undef(tx->regs.oPts))
1328 tx->regs.oPts = ureg_DECL_temporary(tx->ureg);
1329 dst = tx->regs.oPts;
1338 if (tx->version.major < 3) {
1340 dst = ureg_DECL_output(tx->ureg, tx->texcoord_sn, param->idx);
1343 assert(param->idx < ARRAY_SIZE(tx->regs.o));
1344 dst = tx->regs.o[param->idx];
1351 tx->info->rt_mask |= 1 << param->idx;
1352 if (ureg_dst_is_undef(tx->regs.oCol[param->idx])) {
1354 if (!IS_VS && tx->version.major < 3 && param->idx == 0) {
1355 tx->regs.oCol[0] = ureg_DECL_temporary(tx->ureg);
1357 tx->regs.oCol[param->idx] =
1358 ureg_DECL_output(tx->ureg, TGSI_SEMANTIC_COLOR, param->idx);
1361 dst = tx->regs.oCol[param->idx];
1362 if (IS_VS && tx->version.major < 3)
1367 if (ureg_dst_is_undef(tx->regs.oDepth))
1368 tx->regs.oDepth =
1369 ureg_DECL_output_masked(tx->ureg, TGSI_SEMANTIC_POSITION, 0,
1371 dst = tx->regs.oDepth; /* XXX: must write .z component */
1374 if (ureg_dst_is_undef(tx->regs.predicate))
1375 tx->regs.predicate = ureg_DECL_temporary(tx->ureg);
1376 dst = tx->regs.predicate;
1386 dst = ureg_dst_indirect(dst, tx_src_param(tx, param->rel));
1393 if (tx->predicated_activated) {
1394 tx->regs.predicate_dst = dst;
1395 dst = tx->regs.predicate_tmp;
1402 tx_dst_param(struct shader_translator *tx, const struct sm1_dst_param *param)
1405 tx->regs.tdst = ureg_writemask(tx_scratch(tx), param->mask);
1406 return tx->regs.tdst;
1408 return _tx_dst_param(tx, param);
1412 tx_apply_dst0_modifiers(struct shader_translator *tx)
1417 if (!tx->insn.ndst || !tx->insn.dst[0].shift || tx->insn.opcode == D3DSIO_TEXKILL)
1419 rdst = _tx_dst_param(tx, &tx->insn.dst[0]);
1423 if (tx->insn.dst[0].shift < 0)
1424 f = 1.0f / (1 << -tx->insn.dst[0].shift);
1426 f = 1 << tx->insn.dst[0].shift;
1428 ureg_MUL(tx->ureg, rdst, ureg_src(tx->regs.tdst), ureg_imm1f(tx->ureg, f));
1432 tx_dst_param_as_src(struct shader_translator *tx, const struct sm1_dst_param *param)
1445 assert(param->idx < ARRAY_SIZE(tx->regs.v));
1446 src = tx->regs.v[param->idx];
1450 src = ureg_src(tx_dst_param(tx, param));
1454 src = ureg_src_indirect(src, tx_src_param(tx, param->rel));
1475 NineTranslateInstruction_Mkxn(struct shader_translator *tx, const unsigned k, const unsigned n)
1477 struct ureg_program *ureg = tx->ureg;
1480 struct sm1_src_param *src_mat = &tx->insn.src[1];
1483 dst = tx_dst_param(tx, &tx->insn.dst[0]);
1484 src[0] = tx_src_param(tx, &tx->insn.src[0]);
1490 src[1] = tx_src_param(tx, src_mat);
1642 NineTranslateInstruction_##name( struct shader_translator *tx )
1656 struct ureg_program *ureg = tx->ureg;
1657 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
1658 struct ureg_src src0 = tx_src_param(tx, &tx->insn.src[0]);
1659 struct ureg_src src1 = tx_src_param(tx, &tx->insn.src[1]);
1667 struct ureg_program *ureg = tx->ureg;
1668 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
1669 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
1677 struct ureg_program *ureg = tx->ureg;
1678 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
1679 struct ureg_src src0 = tx_src_param(tx, &tx->insn.src[0]);
1680 struct ureg_src src1 = tx_src_param(tx, &tx->insn.src[1]);
1700 return NineTranslateInstruction_Mkxn(tx, 4, 4);
1705 return NineTranslateInstruction_Mkxn(tx, 4, 3);
1710 return NineTranslateInstruction_Mkxn(tx, 3, 4);
1715 return NineTranslateInstruction_Mkxn(tx, 3, 3);
1720 return NineTranslateInstruction_Mkxn(tx, 3, 2);
1725 ureg_CMP(tx->ureg, tx_dst_param(tx, &tx->insn.dst[0]),
1726 tx_src_param(tx, &tx->insn.src[0]),
1727 tx_src_param(tx, &tx->insn.src[2]),
1728 tx_src_param(tx, &tx->insn.src[1]));
1734 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
1744 if (tx->insn.coissue && tx->version.major == 1 && tx->version.minor < 4 && tx->insn.dst[0].mask != NINED3DSP_WRITEMASK_3) {
1745 ureg_MOV(tx->ureg,
1746 dst, tx_src_param(tx, &tx->insn.src[1]));
1750 cnd = tx_src_param(tx, &tx->insn.src[0]);
1751 cgt = tx_scratch(tx);
1753 if (tx->version.major == 1 && tx->version.minor < 4)
1756 ureg_SGT(tx->ureg, cgt, cnd, ureg_imm1f(tx->ureg, 0.5f));
1758 ureg_CMP(tx->ureg, dst, ureg_negate(ureg_src(cgt)),
1759 tx_src_param(tx, &tx->insn.src[1]),
1760 tx_src_param(tx, &tx->insn.src[2]));
1766 assert(tx->insn.src[0].idx < tx->num_inst_labels);
1767 ureg_CAL(tx->ureg, &tx->inst_labels[tx->insn.src[0].idx]);
1773 struct ureg_program *ureg = tx->ureg;
1774 struct ureg_src src = tx_src_param(tx, &tx->insn.src[1]);
1776 if (!tx->native_integers)
1777 ureg_IF(ureg, src, tx_cond(tx));
1779 ureg_UIF(ureg, src, tx_cond(tx));
1780 ureg_CAL(ureg, &tx->inst_labels[tx->insn.src[0].idx]);
1781 tx_endcond(tx);
1788 struct ureg_program *ureg = tx->ureg;
1790 struct ureg_src src = tx_src_param(tx, &tx->insn.src[1]);
1795 label = tx_bgnloop(tx);
1796 ctr = tx_get_loopctr(tx, TRUE);
1801 ureg_BGNLOOP(tx->ureg, label);
1802 tmp = tx_scratch_scalar(tx);
1808 if (!tx->native_integers) {
1812 ureg_IF(ureg, tx_src_scalar(tmp), tx_cond(tx));
1816 ureg_UIF(ureg, tx_src_scalar(tmp), tx_cond(tx));
1819 tx_endcond(tx);
1830 if (*(tx->parse_next) != NINED3DSP_END) {
1831 ureg_RET(tx->ureg);
1838 struct ureg_program *ureg = tx->ureg;
1839 struct ureg_dst ctr = tx_get_loopctr(tx, TRUE);
1850 if (!tx->native_integers) {
1857 ureg_ENDLOOP(tx->ureg, tx_endloop(tx));
1863 unsigned k = tx->num_inst_labels;
1864 unsigned n = tx->insn.src[0].idx;
1867 tx->inst_labels = REALLOC(tx->inst_labels,
1868 k * sizeof(tx->inst_labels[0]),
1869 n * sizeof(tx->inst_labels[0]));
1871 tx->inst_labels[n] = ureg_get_instruction_number(tx->ureg);
1877 struct ureg_program *ureg = tx->ureg;
1878 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
1879 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
1880 struct ureg_dst tmp = tx_scratch_scalar(tx);
1898 ureg_SSG(tx->ureg,
1899 tx_dst_param(tx, &tx->insn.dst[0]),
1900 tx_src_param(tx, &tx->insn.src[0]));
1906 struct ureg_program *ureg = tx->ureg;
1908 struct ureg_src rep = tx_src_param(tx, &tx->insn.src[0]);
1913 label = tx_bgnloop(tx);
1914 ctr = ureg_writemask(tx_get_loopctr(tx, FALSE), NINED3DSP_WRITEMASK_0);
1923 tmp = tx_scratch_scalar(tx);
1928 if (!tx->native_integers) {
1932 ureg_IF(ureg, tx_src_scalar(tmp), tx_cond(tx));
1936 ureg_UIF(ureg, tx_src_scalar(tmp), tx_cond(tx));
1939 tx_endcond(tx);
1947 struct ureg_program *ureg = tx->ureg;
1948 struct ureg_dst ctr = tx_get_loopctr(tx, FALSE);
1953 if (!tx->native_integers)
1958 ureg_ENDLOOP(tx->ureg, tx_endloop(tx));
1964 tx_endcond(tx);
1965 ureg_ENDIF(tx->ureg);
1971 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
1973 if (tx->native_integers && tx->insn.src[0].file == D3DSPR_CONSTBOOL)
1974 ureg_UIF(tx->ureg, src, tx_cond(tx));
1976 ureg_IF(tx->ureg, src, tx_cond(tx));
1999 const unsigned cmp_op = sm1_insn_flags_to_tgsi_setop(tx->insn.flags);
2001 struct ureg_dst tmp = ureg_writemask(tx_scratch(tx), TGSI_WRITEMASK_X);
2002 src[0] = tx_src_param(tx, &tx->insn.src[0]);
2003 src[1] = tx_src_param(tx, &tx->insn.src[1]);
2004 ureg_insn(tx->ureg, cmp_op, &tmp, 1, src, 2, 0);
2005 ureg_IF(tx->ureg, ureg_scalar(ureg_src(tmp), TGSI_SWIZZLE_X), tx_cond(tx));
2011 ureg_ELSE(tx->ureg, tx_elsecond(tx));
2017 const unsigned cmp_op = sm1_insn_flags_to_tgsi_setop(tx->insn.flags);
2019 struct ureg_dst tmp = ureg_writemask(tx_scratch(tx), TGSI_WRITEMASK_X);
2020 src[0] = tx_src_param(tx, &tx->insn.src[0]);
2021 src[1] = tx_src_param(tx, &tx->insn.src[1]);
2022 ureg_insn(tx->ureg, cmp_op, &tmp, 1, src, 2, 0);
2023 ureg_IF(tx->ureg, ureg_scalar(ureg_src(tmp), TGSI_SWIZZLE_X), tx_cond(tx));
2024 ureg_BRK(tx->ureg);
2025 tx_endcond(tx);
2026 ureg_ENDIF(tx->ureg);
2242 struct ureg_program *ureg = tx->ureg;
2247 sm1_read_semantic(tx, &sem);
2258 if (tx->version.major >= 3)
2269 tx->info->sampler_mask |= m;
2270 tx->sampler_targets[sem.reg.idx] = (tx->info->sampler_mask_shadow & m) ?
2276 sm1_declusage_to_tgsi(&tgsi, tx->want_texcoord, &sem);
2281 assert(sem.reg.idx < ARRAY_SIZE(tx->info->input_map));
2282 tx->info->input_map[sem.reg.idx] = sm1_to_nine_declusage(&sem);
2283 tx->info->num_inputs = MAX2(tx->info->num_inputs, sem.reg.idx + 1);
2286 if (tx->version.major >= 3) {
2290 tx->info->position_t = TRUE;
2291 assert(sem.reg.idx < ARRAY_SIZE(tx->regs.o));
2292 assert(ureg_dst_is_undef(tx->regs.o[sem.reg.idx]) && "Nine doesn't support yet packing");
2293 tx->regs.o[sem.reg.idx] = ureg_DECL_output_masked(
2295 nine_record_outputs(tx, sem.usage, sem.usage_idx, sem.reg.mask, sem.reg.idx);
2296 if (tx->info->process_vertices && sem.usage == D3DDECLUSAGE_POSITION && sem.usage_idx == 0) {
2297 tx->regs.oPos_out = tx->regs.o[sem.reg.idx];
2298 tx->regs.o[sem.reg.idx] = ureg_DECL_temporary(ureg);
2299 tx->regs.oPos = tx->regs.o[sem.reg.idx];
2303 tx->regs.o[sem.reg.idx] = ureg_DECL_temporary(ureg);
2304 tx->regs.oPts = tx->regs.o[sem.reg.idx];
2308 if (is_input && tx->version.major >= 3) {
2311 assert(sem.reg.idx < ARRAY_SIZE(tx->regs.v));
2312 assert(ureg_src_is_undef(tx->regs.v[sem.reg.idx]) && "Nine doesn't support yet packing");
2322 tx->regs.v[sem.reg.idx] = nine_get_position_input(tx);
2327 (tgsi.Name == TGSI_SEMANTIC_COLOR && tx->info->force_color_in_centroid))
2330 tx->regs.v[sem.reg.idx] = ureg_DECL_fs_input_centroid(
2347 tx_set_lconstf(tx, tx->insn.dst[0].idx, tx->insn.src[0].imm.f);
2353 tx_set_lconstb(tx, tx->insn.dst[0].idx, tx->insn.src[0].imm.b);
2359 tx_set_lconsti(tx, tx->insn.dst[0].idx, tx->insn.src[0].imm.i);
2365 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2367 tx_src_param(tx, &tx->insn.src[0]),
2368 tx_src_param(tx, &tx->insn.src[1])
2370 ureg_POW(tx->ureg, dst, ureg_abs(src[0]), src[1]);
2405 struct ureg_program *ureg = tx->ureg;
2406 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2407 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
2408 struct ureg_dst tmp = tx->mul_zero_wins ? dst : tx_scratch(tx);
2410 if (!tx->mul_zero_wins) {
2420 struct ureg_program *ureg = tx->ureg;
2421 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2422 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
2423 struct ureg_dst tmp = tx->mul_zero_wins ? dst : tx_scratch(tx);
2425 if (!tx->mul_zero_wins)
2432 struct ureg_program *ureg = tx->ureg;
2433 struct ureg_dst tmp = tx_scratch_scalar(tx);
2434 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2435 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
2437 if (tx->mul_zero_wins) {
2447 struct ureg_program *ureg = tx->ureg;
2448 struct ureg_dst tmp = tx_scratch(tx);
2449 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2450 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
2464 struct ureg_program *ureg = tx->ureg;
2465 struct ureg_dst tmp = tx_scratch_scalar(tx);
2467 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2468 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
2471 if (!tx->mul_zero_wins)
2479 struct ureg_dst tmp = tx_scratch_scalar(tx);
2481 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2485 src[i] = tx_src_param(tx, &tx->insn.src[i]);
2488 ureg_DP2(tx->ureg, tmp, src[0], src[1]);
2489 ureg_ADD(tx->ureg, dst, src[2], dp2);
2496 struct ureg_program *ureg = tx->ureg;
2497 const unsigned s = tx->insn.dst[0].idx;
2498 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2500 tx_texcoord_alloc(tx, s);
2501 ureg_MOV(ureg, ureg_writemask(ureg_saturate(dst), TGSI_WRITEMASK_XYZ), tx->regs.vT[s]);
2502 ureg_MOV(ureg, ureg_writemask(dst, TGSI_WRITEMASK_W), ureg_imm1f(tx->ureg, 1.0f));
2509 struct ureg_program *ureg = tx->ureg;
2510 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
2511 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2513 assert(tx->insn.src[0].file == D3DSPR_TEXTURE);
2524 if (tx->version.major > 1 || tx->version.minor > 3) {
2525 reg = tx_dst_param_as_src(tx, &tx->insn.dst[0]);
2527 tx_texcoord_alloc(tx, tx->insn.dst[0].idx);
2528 reg = tx->regs.vT[tx->insn.dst[0].idx];
2530 if (tx->version.major < 2)
2532 ureg_KILL_IF(tx->ureg, reg);
2539 struct ureg_program *ureg = tx->ureg;
2540 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2541 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2545 const int m = tx->insn.dst[0].idx;
2547 assert(tx->version.major == 1);
2550 tx->info->sampler_mask |= 1 << m;
2552 tx_texcoord_alloc(tx, m);
2554 tmp = tx_scratch(tx);
2555 tmp2 = tx_scratch(tx);
2556 texcoord = tx_scratch(tx);
2564 c8m = nine_float_constant_src(tx, 8+m);
2565 c16m2 = nine_float_constant_src(tx, 8+8+m/2);
2581 apply_ps1x_projection(tx, texcoord, tx->regs.vT[m], m);
2601 if (tx->insn.opcode == D3DSIO_TEXBEM) {
2602 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m), ureg_src(tmp), sample);
2603 } else if (tx->insn.opcode == D3DSIO_TEXBEML) {
2605 ureg_TEX(ureg, tmp, ps1x_sampler_type(tx->info, m), ureg_src(tmp), sample);
2611 tx->info->bumpenvmat_needed = 1;
2618 struct ureg_program *ureg = tx->ureg;
2619 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2620 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2622 const int m = tx->insn.dst[0].idx;
2623 ASSERTED const int n = tx->insn.src[0].idx;
2627 tx->info->sampler_mask |= 1 << m;
2628 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m), ureg_swizzle(src, NINE_SWIZZLE4(W,X,X,X)), sample);
2635 struct ureg_program *ureg = tx->ureg;
2636 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2637 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2639 const int m = tx->insn.dst[0].idx;
2640 ASSERTED const int n = tx->insn.src[0].idx;
2644 tx->info->sampler_mask |= 1 << m;
2645 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m), ureg_swizzle(src, NINE_SWIZZLE4(Y,Z,Z,Z)), sample);
2657 struct ureg_program *ureg = tx->ureg;
2658 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2659 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2661 const int m = tx->insn.dst[0].idx - 1;
2662 ASSERTED const int n = tx->insn.src[0].idx;
2665 tx_texcoord_alloc(tx, m);
2666 tx_texcoord_alloc(tx, m+1);
2669 ureg_DP3(ureg, ureg_writemask(dst, TGSI_WRITEMASK_X), tx->regs.vT[m], src);
2670 ureg_DP3(ureg, ureg_writemask(dst, TGSI_WRITEMASK_Y), tx->regs.vT[m+1], src);
2673 tx->info->sampler_mask |= 1 << (m + 1);
2674 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m + 1), ureg_src(dst), sample);
2686 struct ureg_program *ureg = tx->ureg;
2687 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2688 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2689 struct ureg_src E = tx_src_param(tx, &tx->insn.src[1]);
2692 const int m = tx->insn.dst[0].idx - 2;
2693 ASSERTED const int n = tx->insn.src[0].idx;
2696 tx_texcoord_alloc(tx, m);
2697 tx_texcoord_alloc(tx, m+1);
2698 tx_texcoord_alloc(tx, m+2);
2700 ureg_DP3(ureg, ureg_writemask(dst, TGSI_WRITEMASK_X), tx->regs.vT[m], src);
2701 ureg_DP3(ureg, ureg_writemask(dst, TGSI_WRITEMASK_Y), tx->regs.vT[m+1], src);
2702 ureg_DP3(ureg, ureg_writemask(dst, TGSI_WRITEMASK_Z), tx->regs.vT[m+2], src);
2705 tx->info->sampler_mask |= 1 << (m + 2);
2706 tmp = ureg_writemask(tx_scratch(tx), TGSI_WRITEMASK_XYZ);
2722 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m + 2), ureg_src(tmp), sample);
2729 struct ureg_program *ureg = tx->ureg;
2730 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2731 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2733 const int m = tx->insn.dst[0].idx;
2734 ASSERTED const int n = tx->insn.src[0].idx;
2738 tx->info->sampler_mask |= 1 << m;
2739 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m), src, sample);
2746 struct ureg_program *ureg = tx->ureg;
2747 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2748 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2751 const int m = tx->insn.dst[0].idx;
2752 ASSERTED const int n = tx->insn.src[0].idx;
2755 tx_texcoord_alloc(tx, m);
2757 tmp = tx_scratch(tx);
2758 ureg_DP3(ureg, ureg_writemask(tmp, TGSI_WRITEMASK_X), tx->regs.vT[m], src);
2762 tx->info->sampler_mask |= 1 << m;
2763 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m), ureg_src(tmp), sample);
2770 struct ureg_program *ureg = tx->ureg;
2771 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2773 const int m = tx->insn.dst[0].idx - 1;
2774 ASSERTED const int n = tx->insn.src[0].idx;
2777 tx_texcoord_alloc(tx, m);
2778 tx_texcoord_alloc(tx, m+1);
2780 tmp = tx_scratch(tx);
2783 ureg_DP3(ureg, ureg_writemask(tmp, TGSI_WRITEMASK_X), tx->regs.vT[m], src);
2784 ureg_DP3(ureg, ureg_writemask(tmp, TGSI_WRITEMASK_Y), tx->regs.vT[m+1], src);
2793 tx->regs.oDepth = ureg_DECL_output_masked(ureg, TGSI_SEMANTIC_POSITION, 0,
2795 ureg_MOV(ureg, tx->regs.oDepth, ureg_scalar(ureg_src(tmp), TGSI_SWIZZLE_X));
2802 struct ureg_program *ureg = tx->ureg;
2803 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2804 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2805 const int m = tx->insn.dst[0].idx;
2806 ASSERTED const int n = tx->insn.src[0].idx;
2809 tx_texcoord_alloc(tx, m);
2811 ureg_DP3(ureg, dst, tx->regs.vT[m], src);
2818 struct ureg_program *ureg = tx->ureg;
2819 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2820 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2823 const int m = tx->insn.dst[0].idx - 2;
2824 ASSERTED const int n = tx->insn.src[0].idx;
2827 tx_texcoord_alloc(tx, m);
2828 tx_texcoord_alloc(tx, m+1);
2829 tx_texcoord_alloc(tx, m+2);
2831 ureg_DP3(ureg, ureg_writemask(dst, TGSI_WRITEMASK_X), tx->regs.vT[m], src);
2832 ureg_DP3(ureg, ureg_writemask(dst, TGSI_WRITEMASK_Y), tx->regs.vT[m+1], src);
2833 ureg_DP3(ureg, ureg_writemask(dst, TGSI_WRITEMASK_Z), tx->regs.vT[m+2], src);
2835 switch (tx->insn.opcode) {
2841 tx->info->sampler_mask |= 1 << (m + 2);
2842 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m + 2), ureg_src(dst), sample);
2846 tx->info->sampler_mask |= 1 << (m + 2);
2847 E = tx_scratch(tx);
2848 tmp = ureg_writemask(tx_scratch(tx), TGSI_WRITEMASK_XYZ);
2849 ureg_MOV(ureg, ureg_writemask(E, TGSI_WRITEMASK_X), ureg_scalar(tx->regs.vT[m], TGSI_SWIZZLE_W));
2850 ureg_MOV(ureg, ureg_writemask(E, TGSI_WRITEMASK_Y), ureg_scalar(tx->regs.vT[m+1], TGSI_SWIZZLE_W));
2851 ureg_MOV(ureg, ureg_writemask(E, TGSI_WRITEMASK_Z), ureg_scalar(tx->regs.vT[m+2], TGSI_SWIZZLE_W));
2866 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m + 2), ureg_src(tmp), sample);
2876 struct ureg_program *ureg = tx->ureg;
2880 assert(tx->insn.dst[0].idx == 5); /* instruction must get r5 here */
2884 r5 = tx->regs.r[5];
2894 tx->regs.oDepth = ureg_DECL_output_masked(ureg, TGSI_SEMANTIC_POSITION, 0,
2896 ureg_MOV(ureg, tx->regs.oDepth, r5r);
2903 struct ureg_program *ureg = tx->ureg;
2904 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2905 struct ureg_src src0 = tx_src_param(tx, &tx->insn.src[0]);
2906 struct ureg_src src1 = tx_src_param(tx, &tx->insn.src[1]);
2908 const int m = tx->insn.dst[0].idx;
2909 struct ureg_dst tmp = tx_scratch(tx);
2917 c8m = nine_float_constant_src(tx, 8+m);
2937 tx->info->bumpenvmat_needed = 1;
2944 struct ureg_program *ureg = tx->ureg;
2946 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2948 tx_src_param(tx, &tx->insn.src[0]),
2949 tx_src_param(tx, &tx->insn.src[1])
2951 assert(tx->insn.src[1].idx >= 0 &&
2952 tx->insn.src[1].idx < ARRAY_SIZE(tx->sampler_targets));
2953 target = tx->sampler_targets[tx->insn.src[1].idx];
2955 if (TEX_if_fetch4(tx, dst, target, src[0], src[1], tx->insn.src[1].idx))
2958 switch (tx->insn.flags) {
2977 struct ureg_program *ureg = tx->ureg;
2978 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2979 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
2980 const unsigned s = tx->insn.dst[0].idx;
2981 const unsigned t = ps1x_sampler_type(tx->info, s);
2983 tx->info->sampler_mask |= 1 << s;
2991 struct ureg_program *ureg = tx->ureg;
2992 const unsigned s = tx->insn.dst[0].idx;
2993 const unsigned t = ps1x_sampler_type(tx->info, s);
2994 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2997 tx_texcoord_alloc(tx, s);
2999 src[0] = tx->regs.vT[s];
3001 tx->info->sampler_mask |= 1 << s;
3003 TEX_with_ps1x_projection(tx, dst, t, src[0], src[1], s);
3011 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
3013 tx_src_param(tx, &tx->insn.src[0]),
3014 tx_src_param(tx, &tx->insn.src[1]),
3015 tx_src_param(tx, &tx->insn.src[2]),
3016 tx_src_param(tx, &tx->insn.src[3])
3018 assert(tx->insn.src[1].idx >= 0 &&
3019 tx->insn.src[1].idx < ARRAY_SIZE(tx->sampler_targets));
3020 target = tx->sampler_targets[tx->insn.src[1].idx];
3022 if (TEX_if_fetch4(tx, dst, target, src[0], src[1], tx->insn.src[1].idx))
3025 ureg_TXD(tx->ureg, dst, target, src[0], src[2], src[3], src[1]);
3032 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
3034 tx_src_param(tx, &tx->insn.src[0]),
3035 tx_src_param(tx, &tx->insn.src[1])
3037 assert(tx->insn.src[1].idx >= 0 &&
3038 tx->insn.src[1].idx < ARRAY_SIZE(tx->sampler_targets));
3039 target = tx->sampler_targets[tx->insn.src[1].idx];
3041 if (TEX_if_fetch4(tx, dst, target, src[0], src[1], tx->insn.src[1].idx))
3044 ureg_TXL(tx->ureg, dst, target, src[0], src[1]);
3050 const unsigned cmp_op = sm1_insn_flags_to_tgsi_setop(tx->insn.flags);
3051 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
3053 tx_src_param(tx, &tx->insn.src[0]),
3054 tx_src_param(tx, &tx->insn.src[1])
3056 ureg_insn(tx->ureg, cmp_op, &dst, 1, src, 2, 0);
3062 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
3063 ureg_IF(tx->ureg, src, tx_cond(tx));
3064 ureg_BRK(tx->ureg);
3065 tx_endcond(tx);
3066 ureg_ENDIF(tx->ureg);
3198 create_op_info_map(struct shader_translator *tx)
3200 const unsigned version = (tx->version.major << 8) | tx->version.minor;
3203 for (i = 0; i < ARRAY_SIZE(tx->op_info_map); ++i)
3204 tx->op_info_map[i] = -1;
3206 if (tx->processor == PIPE_SHADER_VERTEX) {
3208 assert(inst_table[i].sio < ARRAY_SIZE(tx->op_info_map));
3211 tx->op_info_map[inst_table[i].sio] = i;
3215 assert(inst_table[i].sio < ARRAY_SIZE(tx->op_info_map));
3218 tx->op_info_map[inst_table[i].sio] = i;
3224 NineTranslateInstruction_Generic(struct shader_translator *tx)
3230 for (i = 0; i < tx->insn.ndst && i < ARRAY_SIZE(dst); ++i)
3231 dst[i] = tx_dst_param(tx, &tx->insn.dst[i]);
3232 for (i = 0; i < tx->insn.nsrc && i < ARRAY_SIZE(src); ++i)
3233 src[i] = tx_src_param(tx, &tx->insn.src[i]);
3235 ureg_insn(tx->ureg, tx->insn.info->opcode,
3236 dst, tx->insn.ndst,
3237 src, tx->insn.nsrc, 0);
3242 TOKEN_PEEK(struct shader_translator *tx)
3244 return *(tx->parse);
3248 TOKEN_NEXT(struct shader_translator *tx)
3250 return *(tx->parse)++;
3254 TOKEN_JUMP(struct shader_translator *tx)
3256 if (tx->parse_next && tx->parse != tx->parse_next) {
3257 WARN("parse(%p) != parse_next(%p) !\n", tx->parse, tx->parse_next);
3258 tx->parse = tx->parse_next;
3263 sm1_parse_eof(struct shader_translator *tx)
3265 return TOKEN_PEEK(tx) == NINED3DSP_END;
3269 sm1_read_version(struct shader_translator *tx)
3271 const DWORD tok = TOKEN_NEXT(tx);
3273 tx->version.major = D3DSHADER_VERSION_MAJOR(tok);
3274 tx->version.minor = D3DSHADER_VERSION_MINOR(tok);
3277 case NINED3D_SM1_VS: tx->processor = PIPE_SHADER_VERTEX; break;
3278 case NINED3D_SM1_PS: tx->processor = PIPE_SHADER_FRAGMENT; break;
3281 tx->processor = ~0;
3288 sm1_parse_get_skip(struct shader_translator *tx)
3290 const DWORD tok = TOKEN_PEEK(tx);
3292 if (tx->version.major >= 2) {
3293 tx->parse_next = tx->parse + 1 /* this */ +
3296 tx->parse_next = NULL; /* TODO: determine from param count */
3309 sm1_parse_comments(struct shader_translator *tx, BOOL print)
3311 DWORD tok = TOKEN_PEEK(tx);
3317 tx->parse += size + 1;
3322 tok = TOKEN_PEEK(tx);
3327 sm1_parse_get_param(struct shader_translator *tx, DWORD *reg, DWORD *rel)
3329 *reg = TOKEN_NEXT(tx);
3333 if (tx->version.major < 2)
3339 *rel = TOKEN_NEXT(tx);
3381 sm1_parse_immediate(struct shader_translator *tx,
3389 switch (tx->insn.opcode) {
3392 memcpy(&imm->imm.d[0], tx->parse, 4 * sizeof(DWORD));
3393 tx->parse += 4;
3397 memcpy(&imm->imm.d[0], tx->parse, 4 * sizeof(DWORD));
3398 tx->parse += 4;
3402 memcpy(&imm->imm.d[0], tx->parse, 1 * sizeof(DWORD));
3403 tx->parse += 1;
3412 sm1_read_dst_param(struct shader_translator *tx,
3418 sm1_parse_get_param(tx, &tok_dst, &tok_rel);
3427 sm1_read_src_param(struct shader_translator *tx,
3433 sm1_parse_get_param(tx, &tok_src, &tok_rel);
3443 sm1_read_semantic(struct shader_translator *tx,
3446 const DWORD tok_usg = TOKEN_NEXT(tx);
3447 const DWORD tok_dst = TOKEN_NEXT(tx);
3457 sm1_parse_instruction(struct shader_translator *tx)
3459 struct sm1_instruction *insn = &tx->insn;
3465 sm1_parse_comments(tx, TRUE);
3466 sm1_parse_get_skip(tx);
3468 tok = TOKEN_NEXT(tx);
3475 if (insn->opcode < ARRAY_SIZE(tx->op_info_map)) {
3476 int k = tx->op_info_map[insn->opcode];
3487 TOKEN_JUMP(tx);
3498 unsigned ver = (tx->version.major << 8) | tx->version.minor;
3507 sm1_read_dst_param(tx, &insn->dst[i], &insn->dst_rel[i]);
3509 sm1_read_src_param(tx, &insn->pred, NULL);
3511 sm1_read_src_param(tx, &insn->src[i], &insn->src_rel[i]);
3517 sm1_parse_immediate(tx, &tx->insn.src[0]);
3519 sm1_dump_instruction(insn, tx->cond_depth + tx->loop_depth);
3523 tx->predicated_activated = true;
3524 if (ureg_dst_is_undef(tx->regs.predicate_tmp)) {
3525 tx->regs.predicate_tmp = ureg_DECL_temporary(tx->ureg);
3526 tx->regs.predicate_dst = ureg_DECL_temporary(tx->ureg);
3531 hr = info->handler(tx);
3533 hr = NineTranslateInstruction_Generic(tx);
3534 tx_apply_dst0_modifiers(tx);
3537 tx->predicated_activated = false;
3540 ureg_CMP(tx->ureg, tx->regs.predicate_dst,
3541 ureg_negate(tx_src_param(tx, &insn->pred)),
3542 ureg_src(tx->regs.predicate_tmp),
3543 ureg_src(tx->regs.predicate_dst));
3547 tx->failure = TRUE;
3548 tx->num_scratch = 0; /* reset */
3550 TOKEN_JUMP(tx);
3559 tx_ctor(struct shader_translator *tx, struct pipe_screen *screen, struct nine_shader_info *info)
3563 memset(tx, 0, sizeof(*tx));
3565 tx->info = info;
3567 tx->byte_code = info->byte_code;
3568 tx->parse = info->byte_code;
3577 memset(tx->slots_used, 0, sizeof(tx->slots_used));
3581 tx->info->const_float_slots = 0;
3582 tx->info->const_int_slots = 0;
3583 tx->info->const_bool_slots = 0;
3593 for (i = 0; i < ARRAY_SIZE(tx->regs.rL); ++i) {
3594 tx->regs.rL[i] = ureg_dst_undef();
3596 tx->regs.address = ureg_dst_undef();
3597 tx->regs.a0 = ureg_dst_undef();
3598 tx->regs.p = ureg_dst_undef();
3599 tx->regs.oDepth = ureg_dst_undef();
3600 tx->regs.vPos = ureg_src_undef();
3601 tx->regs.vFace = ureg_src_undef();
3602 for (i = 0; i < ARRAY_SIZE(tx->regs.o); ++i)
3603 tx->regs.o[i] = ureg_dst_undef();
3604 for (i = 0; i < ARRAY_SIZE(tx->regs.oCol); ++i)
3605 tx->regs.oCol[i] = ureg_dst_undef();
3606 for (i = 0; i < ARRAY_SIZE(tx->regs.vC); ++i)
3607 tx->regs.vC[i] = ureg_src_undef();
3608 for (i = 0; i < ARRAY_SIZE(tx->regs.vT); ++i)
3609 tx->regs.vT[i] = ureg_src_undef();
3611 sm1_read_version(tx);
3613 info->version = (tx->version.major << 4) | tx->version.minor;
3615 tx->num_outputs = 0;
3617 create_op_info_map(tx);
3619 tx->ureg = ureg_create(info->type);
3620 if (!tx->ureg) {
3624 tx->native_integers = GET_SHADER_CAP(INTEGERS);
3625 tx->inline_subroutines = !GET_SHADER_CAP(SUBROUTINES);
3626 tx->want_texcoord = GET_CAP(TGSI_TEXCOORD);
3627 tx->shift_wpos = !GET_CAP(FS_COORD_PIXEL_CENTER_INTEGER);
3628 tx->texcoord_sn = tx->want_texcoord ?
3630 tx->wpos_is_sysval = GET_CAP(FS_POSITION_IS_SYSVAL);
3631 tx->face_is_sysval_integer = GET_CAP(FS_FACE_IS_INTEGER_SYSVAL);
3634 tx->num_constf_allowed = NINE_MAX_CONST_F;
3635 } else if (tx->version.major < 2) {/* IS_PS v1 */
3636 tx->num_constf_allowed = 8;
3637 } else if (tx->version.major == 2) {/* IS_PS v2 */
3638 tx->num_constf_allowed = 32;
3640 tx->num_constf_allowed = NINE_MAX_CONST_F_PS3;
3643 if (tx->version.major < 2) {
3644 tx->num_consti_allowed = 0;
3645 tx->num_constb_allowed = 0;
3647 tx->num_consti_allowed = NINE_MAX_CONST_I;
3648 tx->num_constb_allowed = NINE_MAX_CONST_B;
3652 /* TODO: The values tx->version.major == 1 */
3653 tx->num_constf_allowed = 8192;
3654 tx->num_consti_allowed = 2048;
3655 tx->num_constb_allowed = 2048;
3662 tx->regs.oPos = ureg_DECL_output(tx->ureg, TGSI_SEMANTIC_POSITION, 0);
3664 ureg_property(tx->ureg, TGSI_PROPERTY_FS_COORD_ORIGIN, TGSI_FS_COORD_ORIGIN_UPPER_LEFT);
3665 if (!tx->shift_wpos)
3666 ureg_property(tx->ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
3669 tx->mul_zero_wins = GET_CAP(LEGACY_MATH_RULES);
3670 if (tx->mul_zero_wins)
3671 ureg_property(tx->ureg, TGSI_PROPERTY_LEGACY_MATH_RULES, 1);
3688 tx_set_lconsti(tx, i, info->add_constants_defs.c_combination->const_i[i]);
3694 tx_set_lconstb(tx, i, info->add_constants_defs.c_combination->const_b[i]);
3702 tx_dtor(struct shader_translator *tx)
3704 if (tx->slot_map)
3705 FREE(tx->slot_map);
3706 if (tx->num_inst_labels)
3707 FREE(tx->inst_labels);
3708 FREE(tx->lconstf);
3709 FREE(tx->regs.r);
3710 FREE(tx);
3716 shader_add_vs_viewport_transform(struct shader_translator *tx)
3718 struct ureg_program *ureg = tx->ureg;
3727 * ureg_MUL(ureg, ureg_writemask(pos_tmp, TGSI_WRITEMASK_XYZ), ureg_src(tx->regs.oPos), c0);
3728 * ureg_ADD(ureg, ureg_writemask(tx->regs.oPos_out, TGSI_WRITEMASK_XYZ), ureg_src(pos_tmp), c1);
3730 ureg_MOV(ureg, ureg_writemask(tx->regs.oPos_out, TGSI_WRITEMASK_XYZ), ureg_src(tx->regs.oPos));
3734 shader_add_ps_fog_stage(struct shader_translator *tx, struct ureg_src src_col)
3736 struct ureg_program *ureg = tx->ureg;
3742 if (!tx->info->fog_enable) {
3747 if (tx->info->fog_mode != D3DFOG_NONE) {
3748 depth = tx_scratch_scalar(tx);
3750 ureg_RCP(ureg, depth, ureg_scalar(nine_get_position_input(tx), TGSI_SWIZZLE_W));
3751 ureg_MUL(ureg, depth, ureg_src(depth), ureg_scalar(nine_get_position_input(tx), TGSI_SWIZZLE_Z));
3754 fog_color = nine_float_constant_src(tx, 32);
3755 fog_params = nine_float_constant_src(tx, 33);
3756 fog_factor = tx_scratch_scalar(tx);
3758 if (tx->info->fog_mode == D3DFOG_LINEAR) {
3763 } else if (tx->info->fog_mode == D3DFOG_EXP) {
3768 } else if (tx->info->fog_mode == D3DFOG_EXP2) {
3786 static void parse_shader(struct shader_translator *tx)
3788 struct nine_shader_info *info = tx->info;
3790 while (!sm1_parse_eof(tx) && !tx->failure)
3791 sm1_parse_instruction(tx);
3792 tx->parse++; /* for byte_size */
3794 if (tx->failure)
3797 if (IS_PS && tx->version.major < 3) {
3798 if (tx->version.major < 2) {
3799 assert(tx->num_temp); /* there must be color output */
3801 shader_add_ps_fog_stage(tx, ureg_src(tx->regs.r[0]));
3803 shader_add_ps_fog_stage(tx, ureg_src(tx->regs.oCol[0]));
3807 if (IS_VS && tx->version.major < 3 && ureg_dst_is_undef(tx->regs.oFog) && info->fog_enable) {
3808 tx->regs.oFog = ureg_DECL_output(tx->ureg, TGSI_SEMANTIC_GENERIC, 16);
3809 ureg_MOV(tx->ureg, ureg_writemask(tx->regs.oFog, TGSI_WRITEMASK_X), ureg_imm1f(tx->ureg, 0.0f));
3813 ureg_property(tx->ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, TRUE);
3815 if (IS_VS && !ureg_dst_is_undef(tx->regs.oPts)) {
3816 struct ureg_dst oPts = ureg_DECL_output(tx->ureg, TGSI_SEMANTIC_PSIZE, 0);
3817 ureg_MAX(tx->ureg, tx->regs.oPts, ureg_src(tx->regs.oPts), ureg_imm1f(tx->ureg, info->point_size_min));
3818 ureg_MIN(tx->ureg, oPts, ureg_src(tx->regs.oPts), ureg_imm1f(tx->ureg, info->point_size_max));
3823 shader_add_vs_viewport_transform(tx);
3825 ureg_END(tx->ureg);
3948 struct shader_translator *tx;
3956 tx = MALLOC_STRUCT(shader_translator);
3957 if (!tx)
3960 if (tx_ctor(tx, screen, info) == E_OUTOFMEMORY) {
3967 if (((tx->version.major << 16) | tx->version.minor) > 0x00030000) {
3970 tx->version.major, tx->version.minor);
3973 if (tx->processor != processor) {
3975 DBG("Shader type mismatch: %u / %u !\n", tx->processor, processor);
3979 tx->version.major, tx->version.minor);
3981 parse_shader(tx);
3983 if (tx->failure) {
3988 ureg_destroy(tx->ureg);
3994 if (!tx->indirect_const_access && !info->swvp_on && tx->num_slots > 0) {
4000 ureg_destroy(tx->ureg);
4002 if (tx->num_inst_labels)
4003 FREE(tx->inst_labels);
4004 FREE(tx->lconstf);
4005 FREE(tx->regs.r);
4010 if (tx->slots_used[i]) {
4026 if (tx->slots_used[i]) {
4038 if (tx_ctor(tx, screen, info) == E_OUTOFMEMORY) {
4042 tx->slot_map = slot_map;
4043 parse_shader(tx);
4044 assert(!tx->failure);
4052 assert(j == tx->num_slots);
4057 if (tx->num_lconstf && tx->indirect_const_access) {
4065 data = MALLOC(tx->num_lconstf * 4 * sizeof(float));
4070 indices = MALLOC(tx->num_lconstf * sizeof(indices[0]));
4075 for (n = 0; n < tx->num_lconstf; ++n) {
4076 for (k = 0, i = 0; i < tx->num_lconstf; ++i) {
4077 if (tx->lconstf[i].idx < tx->lconstf[k].idx)
4080 indices[n] = tx->lconstf[k].idx;
4081 memcpy(&data[n * 4], &tx->lconstf[k].f[0], 4 * sizeof(float));
4082 tx->lconstf[k].idx = INT_MAX;
4086 for (n = 1, i = 1; i < tx->num_lconstf; ++i)
4098 for (i = 1; i < tx->num_lconstf; ++i) {
4121 if (tx->indirect_const_access) { /* vs only */
4123 tx->num_slots = MAX2(tx->num_slots, device->max_vs_const_f);
4127 info->const_used_size = sizeof(float[4]) * tx->num_slots;
4128 if (tx->num_slots)
4129 ureg_DECL_constant2D(tx->ureg, 0, tx->num_slots-1, 0);
4131 ureg_DECL_constant2D(tx->ureg, 0, 4095, 0);
4132 ureg_DECL_constant2D(tx->ureg, 0, 4095, 1);
4133 ureg_DECL_constant2D(tx->ureg, 0, 2047, 2);
4134 ureg_DECL_constant2D(tx->ureg, 0, 511, 3);
4138 ureg_DECL_constant2D(tx->ureg, 0, 2, 4); /* Viewport data */
4141 const struct tgsi_token *toks = ureg_get_tokens(tx->ureg, NULL);
4148 tx->output_info,
4149 tx->num_outputs,
4151 info->cso = nine_create_shader_with_so_and_destroy(tx->ureg, pipe, &(info->so));
4153 info->cso = nine_create_shader_with_so_and_destroy(tx->ureg, pipe, NULL);
4163 info->byte_size = (tx->parse - tx->byte_code) * sizeof(DWORD);
4167 tx_dtor(tx);