Lines Matching refs:reg
248 assert_replicate_swizzle(const struct ureg_src *reg)
250 assert(reg->SwizzleY == reg->SwizzleX &&
251 reg->SwizzleZ == reg->SwizzleX &&
252 reg->SwizzleW == reg->SwizzleX);
335 struct sm1_dst_param reg;
430 struct ureg_src reg;
653 *src = tx->lconstf[i].reg;
670 *src = tx->lconsti[i].reg;
687 *src = tx->lconstb[i].reg;
714 tx->lconstf[n].reg = ureg_imm4f(tx->ureg, f[0], f[1], f[2], f[3]);
739 tx->lconsti[n].reg = tx->native_integers ?
764 tx->lconstb[n].reg = tx->native_integers ?
2249 is_input = sem.reg.file == D3DSPR_INPUT;
2251 sem.usage == D3DDECLUSAGE_SAMPLE || sem.reg.file == D3DSPR_SAMPLER;
2254 sm1_dump_dst_param(&sem.reg);
2267 const unsigned m = 1 << sem.reg.idx;
2268 ureg_DECL_sampler(ureg, sem.reg.idx);
2270 tx->sampler_targets[sem.reg.idx] = (tx->info->sampler_mask_shadow & m) ?
2280 ureg_DECL_vs_input(ureg, sem.reg.idx);
2281 assert(sem.reg.idx < ARRAY_SIZE(tx->info->input_map));
2282 tx->info->input_map[sem.reg.idx] = sm1_to_nine_declusage(&sem);
2283 tx->info->num_inputs = MAX2(tx->info->num_inputs, sem.reg.idx + 1);
2288 assert(sem.reg.mask != 0);
2291 assert(sem.reg.idx < ARRAY_SIZE(tx->regs.o));
2292 assert(ureg_dst_is_undef(tx->regs.o[sem.reg.idx]) && "Nine doesn't support yet packing");
2293 tx->regs.o[sem.reg.idx] = ureg_DECL_output_masked(
2294 ureg, tgsi.Name, tgsi.Index, sem.reg.mask, 0, 1);
2295 nine_record_outputs(tx, sem.usage, sem.usage_idx, sem.reg.mask, sem.reg.idx);
2297 tx->regs.oPos_out = tx->regs.o[sem.reg.idx];
2298 tx->regs.o[sem.reg.idx] = ureg_DECL_temporary(ureg);
2299 tx->regs.oPos = tx->regs.o[sem.reg.idx];
2303 tx->regs.o[sem.reg.idx] = ureg_DECL_temporary(ureg);
2304 tx->regs.oPts = tx->regs.o[sem.reg.idx];
2311 assert(sem.reg.idx < ARRAY_SIZE(tx->regs.v));
2312 assert(ureg_src_is_undef(tx->regs.v[sem.reg.idx]) && "Nine doesn't support yet packing");
2322 tx->regs.v[sem.reg.idx] = nine_get_position_input(tx);
2326 if (sem.reg.mod & NINED3DSPDM_CENTROID ||
2330 tx->regs.v[sem.reg.idx] = ureg_DECL_fs_input_centroid(
2337 assert(sem.reg.mask != 0);
2338 ureg_DECL_output_masked(ureg, tgsi.Name, tgsi.Index, sem.reg.mask,
2522 struct ureg_src reg;
2525 reg = tx_dst_param_as_src(tx, &tx->insn.dst[0]);
2528 reg = tx->regs.vT[tx->insn.dst[0].idx];
2531 reg = ureg_swizzle(reg, NINE_SWIZZLE4(X,Y,Z,Z));
2532 ureg_KILL_IF(tx->ureg, reg);
3327 sm1_parse_get_param(struct shader_translator *tx, DWORD *reg, DWORD *rel)
3329 *reg = TOKEN_NEXT(tx);
3331 if (*reg & D3DSHADER_ADDRMODE_RELATIVE)
3453 sm1_parse_dst_param(&sem->reg, tok_dst);