Lines Matching defs:insn
380 sm1_dump_instruction(struct sm1_instruction *insn, unsigned indent)
385 if (insn->opcode == D3DSIO_DCL)
390 if (insn->predicated) {
392 sm1_dump_src_param(&insn->pred);
395 DUMP("%s", d3dsio_to_string(insn->opcode));
396 if (insn->flags) {
397 switch (insn->opcode) {
399 DUMP(insn->flags == NINED3DSI_TEXLD_PROJECT ? "p" : "b");
402 DUMP("_%x", insn->flags);
406 if (insn->coissue)
410 for (i = 0; i < insn->ndst && i < ARRAY_SIZE(insn->dst); ++i) {
411 sm1_dump_dst_param(&insn->dst[i]);
415 for (i = 0; i < insn->nsrc && i < ARRAY_SIZE(insn->src); ++i) {
416 sm1_dump_src_param(&insn->src[i]);
419 if (insn->opcode == D3DSIO_DEF ||
420 insn->opcode == D3DSIO_DEFI ||
421 insn->opcode == D3DSIO_DEFB)
422 sm1_dump_immediate(&insn->src[0]);
461 struct sm1_instruction insn; /* current instruction */
536 sm1_instruction_check(const struct sm1_instruction *insn)
538 if (insn->opcode == D3DSIO_CRS)
540 if (insn->dst[0].mask & NINED3DSP_WRITEMASK_3)
1303 if (!IS_VS && tx->insn.opcode == D3DSIO_TEXKILL) { /* maybe others, too */
1417 if (!tx->insn.ndst || !tx->insn.dst[0].shift || tx->insn.opcode == D3DSIO_TEXKILL)
1419 rdst = _tx_dst_param(tx, &tx->insn.dst[0]);
1423 if (tx->insn.dst[0].shift < 0)
1424 f = 1.0f / (1 << -tx->insn.dst[0].shift);
1426 f = 1 << tx->insn.dst[0].shift;
1480 struct sm1_src_param *src_mat = &tx->insn.src[1];
1483 dst = tx_dst_param(tx, &tx->insn.dst[0]);
1484 src[0] = tx_src_param(tx, &tx->insn.src[0]);
1657 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
1658 struct ureg_src src0 = tx_src_param(tx, &tx->insn.src[0]);
1659 struct ureg_src src1 = tx_src_param(tx, &tx->insn.src[1]);
1668 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
1669 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
1678 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
1679 struct ureg_src src0 = tx_src_param(tx, &tx->insn.src[0]);
1680 struct ureg_src src1 = tx_src_param(tx, &tx->insn.src[1]);
1725 ureg_CMP(tx->ureg, tx_dst_param(tx, &tx->insn.dst[0]),
1726 tx_src_param(tx, &tx->insn.src[0]),
1727 tx_src_param(tx, &tx->insn.src[2]),
1728 tx_src_param(tx, &tx->insn.src[1]));
1734 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
1744 if (tx->insn.coissue && tx->version.major == 1 && tx->version.minor < 4 && tx->insn.dst[0].mask != NINED3DSP_WRITEMASK_3) {
1746 dst, tx_src_param(tx, &tx->insn.src[1]));
1750 cnd = tx_src_param(tx, &tx->insn.src[0]);
1759 tx_src_param(tx, &tx->insn.src[1]),
1760 tx_src_param(tx, &tx->insn.src[2]));
1766 assert(tx->insn.src[0].idx < tx->num_inst_labels);
1767 ureg_CAL(tx->ureg, &tx->inst_labels[tx->insn.src[0].idx]);
1774 struct ureg_src src = tx_src_param(tx, &tx->insn.src[1]);
1780 ureg_CAL(ureg, &tx->inst_labels[tx->insn.src[0].idx]);
1790 struct ureg_src src = tx_src_param(tx, &tx->insn.src[1]);
1864 unsigned n = tx->insn.src[0].idx;
1878 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
1879 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
1899 tx_dst_param(tx, &tx->insn.dst[0]),
1900 tx_src_param(tx, &tx->insn.src[0]));
1908 struct ureg_src rep = tx_src_param(tx, &tx->insn.src[0]);
1971 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
1973 if (tx->native_integers && tx->insn.src[0].file == D3DSPR_CONSTBOOL)
1999 const unsigned cmp_op = sm1_insn_flags_to_tgsi_setop(tx->insn.flags);
2002 src[0] = tx_src_param(tx, &tx->insn.src[0]);
2003 src[1] = tx_src_param(tx, &tx->insn.src[1]);
2017 const unsigned cmp_op = sm1_insn_flags_to_tgsi_setop(tx->insn.flags);
2020 src[0] = tx_src_param(tx, &tx->insn.src[0]);
2021 src[1] = tx_src_param(tx, &tx->insn.src[1]);
2347 tx_set_lconstf(tx, tx->insn.dst[0].idx, tx->insn.src[0].imm.f);
2353 tx_set_lconstb(tx, tx->insn.dst[0].idx, tx->insn.src[0].imm.b);
2359 tx_set_lconsti(tx, tx->insn.dst[0].idx, tx->insn.src[0].imm.i);
2365 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2367 tx_src_param(tx, &tx->insn.src[0]),
2368 tx_src_param(tx, &tx->insn.src[1])
2406 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2407 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
2421 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2422 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
2434 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2435 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
2449 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2450 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
2467 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2468 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
2481 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2485 src[i] = tx_src_param(tx, &tx->insn.src[i]);
2497 const unsigned s = tx->insn.dst[0].idx;
2498 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2510 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
2511 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2513 assert(tx->insn.src[0].file == D3DSPR_TEXTURE);
2525 reg = tx_dst_param_as_src(tx, &tx->insn.dst[0]);
2527 tx_texcoord_alloc(tx, tx->insn.dst[0].idx);
2528 reg = tx->regs.vT[tx->insn.dst[0].idx];
2540 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2541 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2545 const int m = tx->insn.dst[0].idx;
2601 if (tx->insn.opcode == D3DSIO_TEXBEM) {
2603 } else if (tx->insn.opcode == D3DSIO_TEXBEML) {
2619 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2620 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2622 const int m = tx->insn.dst[0].idx;
2623 ASSERTED const int n = tx->insn.src[0].idx;
2636 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2637 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2639 const int m = tx->insn.dst[0].idx;
2640 ASSERTED const int n = tx->insn.src[0].idx;
2658 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2659 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2661 const int m = tx->insn.dst[0].idx - 1;
2662 ASSERTED const int n = tx->insn.src[0].idx;
2687 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2688 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2689 struct ureg_src E = tx_src_param(tx, &tx->insn.src[1]);
2692 const int m = tx->insn.dst[0].idx - 2;
2693 ASSERTED const int n = tx->insn.src[0].idx;
2730 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2731 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2733 const int m = tx->insn.dst[0].idx;
2734 ASSERTED const int n = tx->insn.src[0].idx;
2747 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2748 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2751 const int m = tx->insn.dst[0].idx;
2752 ASSERTED const int n = tx->insn.src[0].idx;
2771 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2773 const int m = tx->insn.dst[0].idx - 1;
2774 ASSERTED const int n = tx->insn.src[0].idx;
2803 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2804 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2805 const int m = tx->insn.dst[0].idx;
2806 ASSERTED const int n = tx->insn.src[0].idx;
2819 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2820 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]); /* t[n] */
2823 const int m = tx->insn.dst[0].idx - 2;
2824 ASSERTED const int n = tx->insn.src[0].idx;
2835 switch (tx->insn.opcode) {
2880 assert(tx->insn.dst[0].idx == 5); /* instruction must get r5 here */
2904 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2905 struct ureg_src src0 = tx_src_param(tx, &tx->insn.src[0]);
2906 struct ureg_src src1 = tx_src_param(tx, &tx->insn.src[1]);
2908 const int m = tx->insn.dst[0].idx;
2946 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2948 tx_src_param(tx, &tx->insn.src[0]),
2949 tx_src_param(tx, &tx->insn.src[1])
2951 assert(tx->insn.src[1].idx >= 0 &&
2952 tx->insn.src[1].idx < ARRAY_SIZE(tx->sampler_targets));
2953 target = tx->sampler_targets[tx->insn.src[1].idx];
2955 if (TEX_if_fetch4(tx, dst, target, src[0], src[1], tx->insn.src[1].idx))
2958 switch (tx->insn.flags) {
2978 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2979 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
2980 const unsigned s = tx->insn.dst[0].idx;
2992 const unsigned s = tx->insn.dst[0].idx;
2994 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
3011 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
3013 tx_src_param(tx, &tx->insn.src[0]),
3014 tx_src_param(tx, &tx->insn.src[1]),
3015 tx_src_param(tx, &tx->insn.src[2]),
3016 tx_src_param(tx, &tx->insn.src[3])
3018 assert(tx->insn.src[1].idx >= 0 &&
3019 tx->insn.src[1].idx < ARRAY_SIZE(tx->sampler_targets));
3020 target = tx->sampler_targets[tx->insn.src[1].idx];
3022 if (TEX_if_fetch4(tx, dst, target, src[0], src[1], tx->insn.src[1].idx))
3032 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
3034 tx_src_param(tx, &tx->insn.src[0]),
3035 tx_src_param(tx, &tx->insn.src[1])
3037 assert(tx->insn.src[1].idx >= 0 &&
3038 tx->insn.src[1].idx < ARRAY_SIZE(tx->sampler_targets));
3039 target = tx->sampler_targets[tx->insn.src[1].idx];
3041 if (TEX_if_fetch4(tx, dst, target, src[0], src[1], tx->insn.src[1].idx))
3050 const unsigned cmp_op = sm1_insn_flags_to_tgsi_setop(tx->insn.flags);
3051 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
3053 tx_src_param(tx, &tx->insn.src[0]),
3054 tx_src_param(tx, &tx->insn.src[1])
3062 struct ureg_src src = tx_src_param(tx, &tx->insn.src[0]);
3230 for (i = 0; i < tx->insn.ndst && i < ARRAY_SIZE(dst); ++i)
3231 dst[i] = tx_dst_param(tx, &tx->insn.dst[i]);
3232 for (i = 0; i < tx->insn.nsrc && i < ARRAY_SIZE(src); ++i)
3233 src[i] = tx_src_param(tx, &tx->insn.src[i]);
3235 ureg_insn(tx->ureg, tx->insn.info->opcode,
3236 dst, tx->insn.ndst,
3237 src, tx->insn.nsrc, 0);
3389 switch (tx->insn.opcode) {
3459 struct sm1_instruction *insn = &tx->insn;
3470 insn->opcode = tok & D3DSI_OPCODE_MASK;
3471 insn->flags = (tok & NINED3DSIO_OPCODE_FLAGS_MASK) >> NINED3DSIO_OPCODE_FLAGS_SHIFT;
3472 insn->coissue = !!(tok & D3DSI_COISSUE);
3473 insn->predicated = !!(tok & NINED3DSHADER_INST_PREDICATED);
3475 if (insn->opcode < ARRAY_SIZE(tx->op_info_map)) {
3476 int k = tx->op_info_map[insn->opcode];
3482 if (insn->opcode == D3DSIO_PHASE) info = &inst_phase;
3483 if (insn->opcode == D3DSIO_COMMENT) info = &inst_comment;
3486 DBG("illegal or unhandled opcode: %08x\n", insn->opcode);
3490 insn->info = info;
3491 insn->ndst = info->ndst;
3492 insn->nsrc = info->nsrc;
3506 for (i = 0; i < insn->ndst; ++i)
3507 sm1_read_dst_param(tx, &insn->dst[i], &insn->dst_rel[i]);
3508 if (insn->predicated)
3509 sm1_read_src_param(tx, &insn->pred, NULL);
3510 for (i = 0; i < insn->nsrc; ++i)
3511 sm1_read_src_param(tx, &insn->src[i], &insn->src_rel[i]);
3514 if (insn->opcode == D3DSIO_DEF ||
3515 insn->opcode == D3DSIO_DEFI ||
3516 insn->opcode == D3DSIO_DEFB)
3517 sm1_parse_immediate(tx, &tx->insn.src[0]);
3519 sm1_dump_instruction(insn, tx->cond_depth + tx->loop_depth);
3520 sm1_instruction_check(insn);
3522 if (insn->predicated) {
3536 if (insn->predicated) {
3541 ureg_negate(tx_src_param(tx, &insn->pred)),