Lines Matching defs:info
376 const struct sm1_op_info *info;
384 /* no info stored for these: */
522 struct nine_shader_info *info;
569 if (tx->info->swvp_on && idx >= 4096) {
578 if (!tx->info->swvp_on)
580 if (tx->info->const_float_slots < (idx + 1))
581 tx->info->const_float_slots = idx + 1;
592 if (tx->info->swvp_on) {
596 unsigned slot_idx = tx->info->const_i_base + idx;
602 tx->info->int_slots_used[idx] = TRUE;
607 if (tx->info->const_int_slots < (idx + 1))
608 tx->info->const_int_slots = idx + 1;
620 if (tx->info->swvp_on) {
624 unsigned slot_idx = tx->info->const_b_base + r;
630 tx->info->bool_slots_used[idx] = TRUE;
636 if (tx->info->const_bool_slots < (idx + 1))
637 tx->info->const_bool_slots = idx + 1;
833 if (!(tx->info->fetch4 & (1 << idx)))
858 unsigned dim = 1 + ((tx->info->projected >> (2 * idx)) & 3);
875 unsigned dim = 1 + ((tx->info->projected >> (2 * idx)) & 3);
877 boolean shadow = !!(tx->info->sampler_mask_shadow & (1 << idx));
1053 tx->info->force_color_in_centroid ?
1351 tx->info->rt_mask |= 1 << param->idx;
2185 ps1x_sampler_type(const struct nine_shader_info *info, unsigned stage)
2187 boolean shadow = !!(info->sampler_mask_shadow & (1 << stage));
2188 switch ((info->sampler_ps1xtypes >> (stage * 2)) & 0x3) {
2269 tx->info->sampler_mask |= m;
2270 tx->sampler_targets[sem.reg.idx] = (tx->info->sampler_mask_shadow & m) ?
2281 assert(sem.reg.idx < ARRAY_SIZE(tx->info->input_map));
2282 tx->info->input_map[sem.reg.idx] = sm1_to_nine_declusage(&sem);
2283 tx->info->num_inputs = MAX2(tx->info->num_inputs, sem.reg.idx + 1);
2290 tx->info->position_t = TRUE;
2296 if (tx->info->process_vertices && sem.usage == D3DDECLUSAGE_POSITION && sem.usage_idx == 0) {
2327 (tgsi.Name == TGSI_SEMANTIC_COLOR && tx->info->force_color_in_centroid))
2550 tx->info->sampler_mask |= 1 << m;
2602 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m), ureg_src(tmp), sample);
2605 ureg_TEX(ureg, tmp, ps1x_sampler_type(tx->info, m), ureg_src(tmp), sample);
2611 tx->info->bumpenvmat_needed = 1;
2627 tx->info->sampler_mask |= 1 << m;
2628 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m), ureg_swizzle(src, NINE_SWIZZLE4(W,X,X,X)), sample);
2644 tx->info->sampler_mask |= 1 << m;
2645 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m), ureg_swizzle(src, NINE_SWIZZLE4(Y,Z,Z,Z)), sample);
2673 tx->info->sampler_mask |= 1 << (m + 1);
2674 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m + 1), ureg_src(dst), sample);
2705 tx->info->sampler_mask |= 1 << (m + 2);
2722 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m + 2), ureg_src(tmp), sample);
2738 tx->info->sampler_mask |= 1 << m;
2739 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m), src, sample);
2762 tx->info->sampler_mask |= 1 << m;
2763 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m), ureg_src(tmp), sample);
2841 tx->info->sampler_mask |= 1 << (m + 2);
2842 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m + 2), ureg_src(dst), sample);
2846 tx->info->sampler_mask |= 1 << (m + 2);
2866 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m + 2), ureg_src(tmp), sample);
2937 tx->info->bumpenvmat_needed = 1;
2981 const unsigned t = ps1x_sampler_type(tx->info, s);
2983 tx->info->sampler_mask |= 1 << s;
2993 const unsigned t = ps1x_sampler_type(tx->info, s);
3001 tx->info->sampler_mask |= 1 << s;
3235 ureg_insn(tx->ureg, tx->insn.info->opcode,
3462 const struct sm1_op_info *info = NULL;
3479 info = &inst_table[k];
3482 if (insn->opcode == D3DSIO_PHASE) info = &inst_phase;
3483 if (insn->opcode == D3DSIO_COMMENT) info = &inst_comment;
3485 if (!info) {
3490 insn->info = info;
3491 insn->ndst = info->ndst;
3492 insn->nsrc = info->nsrc;
3496 unsigned min = IS_VS ? info->vert_version.min : info->frag_version.min;
3497 unsigned max = IS_VS ? info->vert_version.max : info->frag_version.max;
3530 if (info->handler)
3531 hr = info->handler(tx);
3556 screen, info->type, PIPE_SHADER_CAP_##n)
3559 tx_ctor(struct shader_translator *tx, struct pipe_screen *screen, struct nine_shader_info *info)
3565 tx->info = info;
3567 tx->byte_code = info->byte_code;
3568 tx->parse = info->byte_code;
3570 for (i = 0; i < ARRAY_SIZE(info->input_map); ++i)
3571 info->input_map[i] = NINE_DECLUSAGE_NONE;
3572 info->num_inputs = 0;
3574 info->position_t = FALSE;
3575 info->point_size = FALSE;
3578 memset(info->int_slots_used, 0, sizeof(info->int_slots_used));
3579 memset(info->bool_slots_used, 0, sizeof(info->bool_slots_used));
3581 tx->info->const_float_slots = 0;
3582 tx->info->const_int_slots = 0;
3583 tx->info->const_bool_slots = 0;
3585 info->sampler_mask = 0x0;
3586 info->rt_mask = 0x0;
3588 info->lconstf.data = NULL;
3589 info->lconstf.ranges = NULL;
3591 info->bumpenvmat_needed = 0;
3613 info->version = (tx->version.major << 4) | tx->version.minor;
3619 tx->ureg = ureg_create(info->type);
3651 if (info->swvp_on) {
3674 if (info->add_constants_defs.c_combination) {
3677 assert(info->add_constants_defs.int_const_added);
3678 assert(info->add_constants_defs.bool_const_added);
3682 if ((*info->add_constants_defs.int_const_added)[i]) {
3684 info->add_constants_defs.c_combination->const_i[i][0],
3685 info->add_constants_defs.c_combination->const_i[i][1],
3686 info->add_constants_defs.c_combination->const_i[i][2],
3687 info->add_constants_defs.c_combination->const_i[i][3]);
3688 tx_set_lconsti(tx, i, info->add_constants_defs.c_combination->const_i[i]);
3692 if ((*info->add_constants_defs.bool_const_added)[i]) {
3693 DBG("Defining const b%i : %i\n", i, (int)(info->add_constants_defs.c_combination->const_b[i] != 0));
3694 tx_set_lconstb(tx, i, info->add_constants_defs.c_combination->const_b[i]);
3742 if (!tx->info->fog_enable) {
3747 if (tx->info->fog_mode != D3DFOG_NONE) {
3758 if (tx->info->fog_mode == D3DFOG_LINEAR) {
3763 } else if (tx->info->fog_mode == D3DFOG_EXP) {
3768 } else if (tx->info->fog_mode == D3DFOG_EXP2) {
3788 struct nine_shader_info *info = tx->info;
3800 info->rt_mask |= 0x1;
3807 if (IS_VS && tx->version.major < 3 && ureg_dst_is_undef(tx->regs.oFog) && info->fog_enable) {
3812 if (info->position_t)
3817 ureg_MAX(tx->ureg, tx->regs.oPts, ureg_src(tx->regs.oPts), ureg_imm1f(tx->ureg, info->point_size_min));
3818 ureg_MIN(tx->ureg, oPts, ureg_src(tx->regs.oPts), ureg_imm1f(tx->ureg, info->point_size_max));
3819 info->point_size = TRUE;
3822 if (info->process_vertices)
3946 nine_translate_shader(struct NineDevice9 *device, struct nine_shader_info *info, struct pipe_context *pipe)
3950 const unsigned processor = info->type;
3951 struct pipe_screen *screen = info->process_vertices ? device->screen_sw : device->screen;
3960 if (tx_ctor(tx, screen, info) == E_OUTOFMEMORY) {
3965 assert(IS_VS || !info->swvp_on);
3994 if (!tx->indirect_const_access && !info->swvp_on && tx->num_slots > 0) {
4038 if (tx_ctor(tx, screen, info) == E_OUTOFMEMORY) {
4068 info->lconstf.data = data;
4094 info->lconstf.ranges = ranges;
4115 if (info->const_float_slots > device->max_vs_const_f &&
4116 (info->const_int_slots || info->const_bool_slots) &&
4117 !info->swvp_on)
4122 info->const_float_slots = device->max_vs_const_f;
4126 if (!info->swvp_on) {
4127 info->const_used_size = sizeof(float[4]) * tx->num_slots;
4137 if (info->process_vertices)
4146 if (info->process_vertices) {
4147 NineVertexDeclaration9_FillStreamOutputInfo(info->vdecl_out,
4150 &(info->so));
4151 info->cso = nine_create_shader_with_so_and_destroy(tx->ureg, pipe, &(info->so));
4153 info->cso = nine_create_shader_with_so_and_destroy(tx->ureg, pipe, NULL);
4154 if (!info->cso) {
4156 FREE(info->lconstf.data);
4157 FREE(info->lconstf.ranges);
4161 info->const_ranges = const_ranges;
4163 info->byte_size = (tx->parse - tx->byte_code) * sizeof(DWORD);