Lines Matching defs:dst
374 struct sm1_dst_param dst[1];
410 for (i = 0; i < insn->ndst && i < ARRAY_SIZE(insn->dst); ++i) {
411 sm1_dump_dst_param(&insn->dst[i]);
484 struct ureg_dst tdst; /* scratch dst if we need extra modifiers */
540 if (insn->dst[0].mask & NINED3DSP_WRITEMASK_3)
788 tx_src_scalar(struct ureg_dst dst)
790 struct ureg_src src = ureg_src(dst);
791 int c = ffs(dst.WriteMask) - 1;
792 if (dst.WriteMask == (1 << c))
826 TEX_if_fetch4(struct shader_translator *tx, struct ureg_dst dst,
841 ureg_MOV(tx->ureg, dst, ureg_swizzle(ureg_src(tmp), NINE_SWIZZLE4(Z, X, Y, W)));
854 apply_ps1x_projection(struct shader_translator *tx, struct ureg_dst dst,
862 ureg_MOV(tx->ureg, dst, src);
866 ureg_MUL(tx->ureg, dst, tx_src_scalar(tmp), src);
871 TEX_with_ps1x_projection(struct shader_translator *tx, struct ureg_dst dst,
884 ureg_TEX(tx->ureg, dst, target, src0, src1);
886 ureg_TXP(tx->ureg, dst, target, src0, src1);
890 ureg_TEX(tx->ureg, dst, target, ureg_src(tmp), src1);
1286 struct ureg_dst dst;
1293 dst = tx->regs.r[param->idx];
1301 dst = tx->regs.tS[param->idx];
1305 dst = ureg_dst(tx->regs.vT[param->idx]);
1308 dst = tx->regs.a0;
1318 dst = tx->regs.oPos;
1324 dst = tx->regs.oFog;
1329 dst = tx->regs.oPts;
1340 dst = ureg_DECL_output(tx->ureg, tx->texcoord_sn, param->idx);
1344 dst = tx->regs.o[param->idx];
1361 dst = tx->regs.oCol[param->idx];
1363 dst = ureg_saturate(dst);
1371 dst = tx->regs.oDepth; /* XXX: must write .z component */
1376 dst = tx->regs.predicate;
1382 assert(!"invalid dst D3DSPR");
1386 dst = ureg_dst_indirect(dst, tx_src_param(tx, param->rel));
1389 dst = ureg_writemask(dst, param->mask);
1391 dst = ureg_saturate(dst);
1394 tx->regs.predicate_dst = dst;
1395 dst = tx->regs.predicate_tmp;
1398 return dst;
1417 if (!tx->insn.ndst || !tx->insn.dst[0].shift || tx->insn.opcode == D3DSIO_TEXKILL)
1419 rdst = _tx_dst_param(tx, &tx->insn.dst[0]);
1423 if (tx->insn.dst[0].shift < 0)
1424 f = 1.0f / (1 << -tx->insn.dst[0].shift);
1426 f = 1 << tx->insn.dst[0].shift;
1478 struct ureg_dst dst;
1483 dst = tx_dst_param(tx, &tx->insn.dst[0]);
1493 if (!(dst.WriteMask & m))
1496 /* XXX: src == dst case ? */
1500 ureg_DP3(ureg, ureg_writemask(dst, m), src[0], src[1]);
1503 ureg_DP4(ureg, ureg_writemask(dst, m), src[0], src[1]);
1657 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
1661 ureg_ADD(ureg, dst, src0, ureg_negate(src1));
1668 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
1671 ureg_MOV(ureg, dst, ureg_abs(src));
1678 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
1682 ureg_MUL(ureg, ureg_writemask(dst, TGSI_WRITEMASK_XYZ),
1687 ureg_MAD(ureg, ureg_writemask(dst, TGSI_WRITEMASK_XYZ),
1692 ureg_src(dst));
1693 ureg_MOV(ureg, ureg_writemask(dst, TGSI_WRITEMASK_W),
1725 ureg_CMP(tx->ureg, tx_dst_param(tx, &tx->insn.dst[0]),
1734 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
1740 * the two executions had same dst with different channels.
1744 if (tx->insn.coissue && tx->version.major == 1 && tx->version.minor < 4 && tx->insn.dst[0].mask != NINED3DSP_WRITEMASK_3) {
1746 dst, tx_src_param(tx, &tx->insn.src[1]));
1758 ureg_CMP(tx->ureg, dst, ureg_negate(ureg_src(cgt)),
1878 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
1882 assert(!(dst.WriteMask & 0xc));
1884 /* Copying to a temporary register avoids src/dst aliasing.
1889 ureg_COS(ureg, ureg_writemask(dst, TGSI_WRITEMASK_X),
1891 ureg_SIN(ureg, ureg_writemask(dst, TGSI_WRITEMASK_Y),
1899 tx_dst_param(tx, &tx->insn.dst[0]),
2347 tx_set_lconstf(tx, tx->insn.dst[0].idx, tx->insn.src[0].imm.f);
2353 tx_set_lconstb(tx, tx->insn.dst[0].idx, tx->insn.src[0].imm.b);
2359 tx_set_lconsti(tx, tx->insn.dst[0].idx, tx->insn.src[0].imm.i);
2365 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2370 ureg_POW(tx->ureg, dst, ureg_abs(src[0]), src[1]);
2406 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2408 struct ureg_dst tmp = tx->mul_zero_wins ? dst : tx_scratch(tx);
2413 ureg_MAX(ureg, dst, ureg_imm1f(ureg, -FLT_MAX/2.f), ureg_src(tmp));
2421 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2423 struct ureg_dst tmp = tx->mul_zero_wins ? dst : tx_scratch(tx);
2426 ureg_MIN(ureg, dst, ureg_imm1f(ureg, FLT_MAX), ureg_src(tmp));
2434 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2438 ureg_MOV(ureg, dst, tx_src_scalar(tmp));
2440 ureg_MAX(ureg, dst, ureg_imm1f(ureg, -FLT_MAX), tx_src_scalar(tmp));
2449 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2453 * states that dst.z is 0 when src.y <= 0. Gallium definition can assign
2455 ureg_CMP(ureg, ureg_writemask(dst, TGSI_WRITEMASK_Z),
2458 ureg_MOV(ureg, ureg_writemask(dst, TGSI_WRITEMASK_XYW), ureg_src(tmp));
2467 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2473 ureg_MUL(ureg, dst, src, nrm);
2481 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2489 ureg_ADD(tx->ureg, dst, src[2], dp2);
2497 const unsigned s = tx->insn.dst[0].idx;
2498 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2501 ureg_MOV(ureg, ureg_writemask(ureg_saturate(dst), TGSI_WRITEMASK_XYZ), tx->regs.vT[s]);
2502 ureg_MOV(ureg, ureg_writemask(dst, TGSI_WRITEMASK_W), ureg_imm1f(tx->ureg, 1.0f));
2511 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2515 ureg_MOV(ureg, dst, src);
2525 reg = tx_dst_param_as_src(tx, &tx->insn.dst[0]);
2527 tx_texcoord_alloc(tx, tx->insn.dst[0].idx);
2528 reg = tx->regs.vT[tx->insn.dst[0].idx];
2540 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2545 const int m = tx->insn.dst[0].idx;
2602 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m), ureg_src(tmp), sample);
2608 ureg_MUL(ureg, dst, ureg_src(tmp), ureg_src(tmp2));
2619 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2622 const int m = tx->insn.dst[0].idx;
2628 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m), ureg_swizzle(src, NINE_SWIZZLE4(W,X,X,X)), sample);
2636 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2639 const int m = tx->insn.dst[0].idx;
2645 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m), ureg_swizzle(src, NINE_SWIZZLE4(Y,Z,Z,Z)), sample);
2658 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2661 const int m = tx->insn.dst[0].idx - 1;
2669 ureg_DP3(ureg, ureg_writemask(dst, TGSI_WRITEMASK_X), tx->regs.vT[m], src);
2670 ureg_DP3(ureg, ureg_writemask(dst, TGSI_WRITEMASK_Y), tx->regs.vT[m+1], src);
2674 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m + 1), ureg_src(dst), sample);
2687 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2692 const int m = tx->insn.dst[0].idx - 2;
2700 ureg_DP3(ureg, ureg_writemask(dst, TGSI_WRITEMASK_X), tx->regs.vT[m], src);
2701 ureg_DP3(ureg, ureg_writemask(dst, TGSI_WRITEMASK_Y), tx->regs.vT[m+1], src);
2702 ureg_DP3(ureg, ureg_writemask(dst, TGSI_WRITEMASK_Z), tx->regs.vT[m+2], src);
2708 /* At this step, dst = N = (u', w', z').
2709 * We want dst to be the texture sampled at (u'', w'', z''), with
2711 ureg_DP3(ureg, ureg_writemask(tmp, TGSI_WRITEMASK_X), ureg_src(dst), ureg_src(dst));
2714 ureg_DP3(ureg, ureg_writemask(tmp, TGSI_WRITEMASK_Y), ureg_src(dst), E);
2719 ureg_MUL(ureg, tmp, ureg_scalar(ureg_src(tmp), TGSI_SWIZZLE_X), ureg_src(dst));
2722 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m + 2), ureg_src(tmp), sample);
2730 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2733 const int m = tx->insn.dst[0].idx;
2739 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m), src, sample);
2747 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2751 const int m = tx->insn.dst[0].idx;
2763 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m), ureg_src(tmp), sample);
2773 const int m = tx->insn.dst[0].idx - 1;
2803 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2805 const int m = tx->insn.dst[0].idx;
2811 ureg_DP3(ureg, dst, tx->regs.vT[m], src);
2819 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2823 const int m = tx->insn.dst[0].idx - 2;
2831 ureg_DP3(ureg, ureg_writemask(dst, TGSI_WRITEMASK_X), tx->regs.vT[m], src);
2832 ureg_DP3(ureg, ureg_writemask(dst, TGSI_WRITEMASK_Y), tx->regs.vT[m+1], src);
2833 ureg_DP3(ureg, ureg_writemask(dst, TGSI_WRITEMASK_Z), tx->regs.vT[m+2], src);
2837 ureg_MOV(ureg, ureg_writemask(dst, TGSI_WRITEMASK_W), ureg_imm1f(ureg, 1.0f));
2842 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m + 2), ureg_src(dst), sample);
2852 /* At this step, dst = N = (u', w', z').
2853 * We want dst to be the texture sampled at (u'', w'', z''), with
2855 ureg_DP3(ureg, ureg_writemask(tmp, TGSI_WRITEMASK_X), ureg_src(dst), ureg_src(dst));
2858 ureg_DP3(ureg, ureg_writemask(tmp, TGSI_WRITEMASK_Y), ureg_src(dst), ureg_src(E));
2863 ureg_MUL(ureg, tmp, ureg_scalar(ureg_src(tmp), TGSI_SWIZZLE_X), ureg_src(dst));
2866 ureg_TEX(ureg, dst, ps1x_sampler_type(tx->info, m + 2), ureg_src(tmp), sample);
2880 assert(tx->insn.dst[0].idx == 5); /* instruction must get r5 here */
2904 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2908 const int m = tx->insn.dst[0].idx;
2935 ureg_MOV(ureg, ureg_writemask(dst, TGSI_WRITEMASK_XY), ureg_src(tmp));
2946 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2955 if (TEX_if_fetch4(tx, dst, target, src[0], src[1], tx->insn.src[1].idx))
2960 ureg_TEX(ureg, dst, target, src[0], src[1]);
2963 ureg_TXP(ureg, dst, target, src[0], src[1]);
2966 ureg_TXB(ureg, dst, target, src[0], src[1]);
2978 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
2980 const unsigned s = tx->insn.dst[0].idx;
2984 ureg_TEX(ureg, dst, t, src, ureg_DECL_sampler(ureg, s));
2992 const unsigned s = tx->insn.dst[0].idx;
2994 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
3003 TEX_with_ps1x_projection(tx, dst, t, src[0], src[1], s);
3011 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
3022 if (TEX_if_fetch4(tx, dst, target, src[0], src[1], tx->insn.src[1].idx))
3025 ureg_TXD(tx->ureg, dst, target, src[0], src[2], src[3], src[1]);
3032 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
3041 if (TEX_if_fetch4(tx, dst, target, src[0], src[1], tx->insn.src[1].idx))
3044 ureg_TXL(tx->ureg, dst, target, src[0], src[1]);
3051 struct ureg_dst dst = tx_dst_param(tx, &tx->insn.dst[0]);
3056 ureg_insn(tx->ureg, cmp_op, &dst, 1, src, 2, 0);
3226 struct ureg_dst dst[1];
3230 for (i = 0; i < tx->insn.ndst && i < ARRAY_SIZE(dst); ++i)
3231 dst[i] = tx_dst_param(tx, &tx->insn.dst[i]);
3236 dst, tx->insn.ndst,
3344 sm1_parse_dst_param(struct sm1_dst_param *dst, DWORD tok)
3347 dst->file =
3350 dst->type = TGSI_RETURN_TYPE_FLOAT;
3351 dst->idx = tok & D3DSP_REGNUM_MASK;
3352 dst->rel = NULL;
3353 dst->mask = (tok & NINED3DSP_WRITEMASK_MASK) >> NINED3DSP_WRITEMASK_SHIFT;
3354 dst->mod = (tok & D3DSP_DSTMOD_MASK) >> D3DSP_DSTMOD_SHIFT;
3356 dst->shift = (shift & 0x7) - (shift & 0x8);
3413 struct sm1_dst_param *dst,
3419 sm1_parse_dst_param(dst, tok_dst);
3422 dst->rel = rel;
3507 sm1_read_dst_param(tx, &insn->dst[i], &insn->dst_rel[i]);