Lines Matching refs:state
206 static void finish_fence(struct rendering_state *state)
210 state->pctx->flush(state->pctx, &handle, 0);
212 state->pctx->screen->fence_finish(state->pctx->screen,
215 state->pctx->screen->fence_reference(state->pctx->screen,
220 get_pcbuf_size(struct rendering_state *state, enum pipe_shader_type pstage)
223 return state->has_pcbuf[pstage] ? state->push_size[is_compute] : 0;
227 calc_ubo0_size(struct rendering_state *state, enum pipe_shader_type pstage)
229 unsigned size = get_pcbuf_size(state, pstage);
230 for (unsigned i = 0; i < state->uniform_blocks[pstage].count; i++)
231 size += state->uniform_blocks[pstage].size[i];
236 fill_ubo0(struct rendering_state *state, uint8_t *mem, enum pipe_shader_type pstage)
238 unsigned push_size = get_pcbuf_size(state, pstage);
240 memcpy(mem, state->push_constants, push_size);
243 for (unsigned i = 0; i < state->uniform_blocks[pstage].count; i++) {
244 unsigned size = state->uniform_blocks[pstage].size[i];
245 memcpy(mem, state->uniform_blocks[pstage].block[i], size);
251 update_pcbuf(struct rendering_state *state, enum pipe_shader_type pstage)
255 unsigned size = calc_ubo0_size(state, pstage);
259 u_upload_alloc(state->uploader, 0, size, 64, &cbuf.buffer_offset, &cbuf.buffer, (void**)&mem);
260 fill_ubo0(state, mem, pstage);
261 state->pctx->set_constant_buffer(state->pctx, pstage, 0, true, &cbuf);
262 state->pcbuf_dirty[pstage] = false;
266 update_inline_shader_state(struct rendering_state *state, enum pipe_shader_type sh, bool pcbuf_dirty, bool constbuf_dirty)
271 state->inlines_dirty[sh] = false;
272 if (!state->pipeline[is_compute]->inlines[stage].can_inline)
274 struct lvp_pipeline *pipeline = state->pipeline[is_compute];
281 unsigned push_size = get_pcbuf_size(state, sh);
285 memcpy(&inline_uniforms[i], &state->push_constants[offset], sizeof(uint32_t));
287 for (unsigned i = 0; i < state->uniform_blocks[sh].count; i++) {
288 if (offset < push_size + state->uniform_blocks[sh].size[i]) {
290 uint8_t *block = state->uniform_blocks[sh].block[i];
294 push_size += state->uniform_blocks[sh].size[i];
304 struct pipe_constant_buffer *cbuf = &state->const_buffer[sh][slot - 1];
309 uint8_t *map = state->pctx->buffer_map(state->pctx, pres, 0, PIPE_MAP_READ, &box, &xfer);
314 state->pctx->buffer_unmap(state->pctx, xfer);
333 state->pctx->bind_vs_state(state->pctx, shader_state);
336 state->pctx->bind_tcs_state(state->pctx, shader_state);
339 state->pctx->bind_tes_state(state->pctx, shader_state);
342 state->pctx->bind_gs_state(state->pctx, shader_state);
345 state->pctx->bind_fs_state(state->pctx, shader_state);
348 state->pctx->bind_compute_state(state->pctx, shader_state);
354 static void emit_compute_state(struct rendering_state *state)
356 if (state->iv_dirty[PIPE_SHADER_COMPUTE]) {
357 state->pctx->set_shader_images(state->pctx, PIPE_SHADER_COMPUTE,
358 0, state->num_shader_images[PIPE_SHADER_COMPUTE],
359 0, state->iv[PIPE_SHADER_COMPUTE]);
360 state->iv_dirty[PIPE_SHADER_COMPUTE] = false;
363 bool pcbuf_dirty = state->pcbuf_dirty[PIPE_SHADER_COMPUTE];
364 if (state->pcbuf_dirty[PIPE_SHADER_COMPUTE])
365 update_pcbuf(state, PIPE_SHADER_COMPUTE);
367 bool constbuf_dirty = state->constbuf_dirty[PIPE_SHADER_COMPUTE];
368 if (state->constbuf_dirty[PIPE_SHADER_COMPUTE]) {
369 for (unsigned i = 0; i < state->num_const_bufs[PIPE_SHADER_COMPUTE]; i++)
370 state->pctx->set_constant_buffer(state->pctx, PIPE_SHADER_COMPUTE,
371 i + 1, false, &state->const_buffer[PIPE_SHADER_COMPUTE][i]);
372 state->constbuf_dirty[PIPE_SHADER_COMPUTE] = false;
375 if (state->inlines_dirty[PIPE_SHADER_COMPUTE])
376 update_inline_shader_state(state, PIPE_SHADER_COMPUTE, pcbuf_dirty, constbuf_dirty);
378 if (state->sb_dirty[PIPE_SHADER_COMPUTE]) {
379 state->pctx->set_shader_buffers(state->pctx, PIPE_SHADER_COMPUTE,
380 0, state->num_shader_buffers[PIPE_SHADER_COMPUTE],
381 state->sb[PIPE_SHADER_COMPUTE], state->access[MESA_SHADER_COMPUTE].buffers_written);
382 state->sb_dirty[PIPE_SHADER_COMPUTE] = false;
385 if (state->sv_dirty[PIPE_SHADER_COMPUTE]) {
386 state->pctx->set_sampler_views(state->pctx, PIPE_SHADER_COMPUTE, 0, state->num_sampler_views[PIPE_SHADER_COMPUTE],
387 0, false, state->sv[PIPE_SHADER_COMPUTE]);
388 state->sv_dirty[PIPE_SHADER_COMPUTE] = false;
391 if (state->ss_dirty[PIPE_SHADER_COMPUTE]) {
392 for (unsigned i = 0; i < state->num_sampler_states[PIPE_SHADER_COMPUTE]; i++) {
393 if (state->ss_cso[PIPE_SHADER_COMPUTE][i])
394 state->pctx->delete_sampler_state(state->pctx, state->ss_cso[PIPE_SHADER_COMPUTE][i]);
395 state->ss_cso[PIPE_SHADER_COMPUTE][i] = state->pctx->create_sampler_state(state->pctx, &state->ss[PIPE_SHADER_COMPUTE][i]);
397 state->pctx->bind_sampler_states(state->pctx, PIPE_SHADER_COMPUTE, 0, state->num_sampler_states[PIPE_SHADER_COMPUTE], state->ss_cso[PIPE_SHADER_COMPUTE]);
398 state->ss_dirty[PIPE_SHADER_COMPUTE] = false;
402 static void emit_state(struct rendering_state *state)
405 if (state->blend_dirty) {
408 if (state->color_write_disables) {
409 u_foreach_bit(att, state->color_write_disables) {
410 mask |= state->blend_state.rt[att].colormask << (att * 4);
411 state->blend_state.rt[att].colormask = 0;
414 cso_set_blend(state->cso, &state->blend_state);
416 if (state->color_write_disables) {
418 u_foreach_bit(att, state->color_write_disables) {
419 state->blend_state.rt[att].colormask = (mask >> (att * 4)) & att_mask;
422 state->blend_dirty = false;
425 if (state->rs_dirty) {
426 bool ms = state->rs_state.multisample;
427 if (state->disable_multisample &&
428 (state->gs_output_lines == GS_OUTPUT_LINES ||
429 (state->gs_output_lines == GS_OUTPUT_NONE && u_reduced_prim(state->info.mode) == PIPE_PRIM_LINES)))
430 state->rs_state.multisample = false;
432 if (state->depth_bias.enabled) {
433 memcpy(&state->rs_state.offset_units, &state->depth_bias, sizeof(float) * 3);
434 state->rs_state.offset_tri = true;
435 state->rs_state.offset_line = true;
436 state->rs_state.offset_point = true;
438 memset(&state->rs_state.offset_units, 0, sizeof(float) * 3);
439 state->rs_state.offset_tri = false;
440 state->rs_state.offset_line = false;
441 state->rs_state.offset_point = false;
443 cso_set_rasterizer(state->cso, &state->rs_state);
444 state->rs_dirty = false;
445 state->rs_state.multisample = ms;
448 if (state->dsa_dirty) {
449 cso_set_depth_stencil_alpha(state->cso, &state->dsa_state);
450 state->dsa_dirty = false;
453 if (state->sample_mask_dirty) {
454 cso_set_sample_mask(state->cso, state->sample_mask);
455 state->sample_mask_dirty = false;
458 if (state->min_samples_dirty) {
459 cso_set_min_samples(state->cso, state->min_samples);
460 state->min_samples_dirty = false;
463 if (state->blend_color_dirty) {
464 state->pctx->set_blend_color(state->pctx, &state->blend_color);
465 state->blend_color_dirty = false;
468 if (state->stencil_ref_dirty) {
469 cso_set_stencil_ref(state->cso, state->stencil_ref);
470 state->stencil_ref_dirty = false;
473 if (state->vb_dirty) {
474 cso_set_vertex_buffers(state->cso, state->start_vb, state->num_vb, 0, false, state->vb);
475 state->vb_dirty = false;
478 if (state->ve_dirty) {
479 cso_set_vertex_elements(state->cso, &state->velem);
480 state->ve_dirty = false;
486 constbuf_dirty[sh] = state->constbuf_dirty[sh];
487 if (state->constbuf_dirty[sh]) {
488 for (unsigned idx = 0; idx < state->num_const_bufs[sh]; idx++)
489 state->pctx->set_constant_buffer(state->pctx, sh,
490 idx + 1, false, &state->const_buffer[sh][idx]);
492 state->constbuf_dirty[sh] = false;
496 pcbuf_dirty[sh] = state->pcbuf_dirty[sh];
497 if (state->pcbuf_dirty[sh])
498 update_pcbuf(state, sh);
502 if (state->inlines_dirty[sh])
503 update_inline_shader_state(state, sh, pcbuf_dirty[sh], constbuf_dirty[sh]);
507 if (state->sb_dirty[sh]) {
508 state->pctx->set_shader_buffers(state->pctx, sh,
509 0, state->num_shader_buffers[sh],
510 state->sb[sh], state->access[tgsi_processor_to_shader_stage(sh)].buffers_written);
515 if (state->iv_dirty[sh]) {
516 state->pctx->set_shader_images(state->pctx, sh,
517 0, state->num_shader_images[sh], 0,
518 state->iv[sh]);
524 if (!state->sv_dirty[sh])
527 state->pctx->set_sampler_views(state->pctx, sh, 0, state->num_sampler_views[sh],
528 0, false, state->sv[sh]);
529 state->sv_dirty[sh] = false;
533 if (!state->ss_dirty[sh])
536 cso_set_samplers(state->cso, sh, state->num_sampler_states[sh], state->cso_ss_ptr[sh]);
539 if (state->vp_dirty) {
540 state->pctx->set_viewport_states(state->pctx, 0, state->num_viewports, state->viewports);
541 state->vp_dirty = false;
544 if (state->scissor_dirty) {
545 state->pctx->set_scissor_states(state->pctx, 0, state->num_scissors, state->scissors);
546 state->scissor_dirty = false;
551 struct rendering_state *state)
556 state->has_pcbuf[PIPE_SHADER_COMPUTE] = pipeline->layout->push_constant_size > 0;
557 state->uniform_blocks[PIPE_SHADER_COMPUTE].count = pipeline->layout->stage[MESA_SHADER_COMPUTE].uniform_block_count;
559 state->uniform_blocks[PIPE_SHADER_COMPUTE].size[j] = pipeline->layout->stage[MESA_SHADER_COMPUTE].uniform_block_sizes[j];
560 if (!state->has_pcbuf[PIPE_SHADER_COMPUTE] && !pipeline->layout->stage[MESA_SHADER_COMPUTE].uniform_block_count)
561 state->pcbuf_dirty[PIPE_SHADER_COMPUTE] = false;
563 state->iv_dirty[MESA_SHADER_COMPUTE] |= state->num_shader_images[MESA_SHADER_COMPUTE] &&
564 (state->access[MESA_SHADER_COMPUTE].images_read != pipeline->access[MESA_SHADER_COMPUTE].images_read ||
565 state->access[MESA_SHADER_COMPUTE].images_written != pipeline->access[MESA_SHADER_COMPUTE].images_written);
566 state->sb_dirty[MESA_SHADER_COMPUTE] |= state->num_shader_buffers[MESA_SHADER_COMPUTE] &&
567 state->access[MESA_SHADER_COMPUTE].buffers_written != pipeline->access[MESA_SHADER_COMPUTE].buffers_written;
568 memcpy(&state->access[MESA_SHADER_COMPUTE], &pipeline->access[MESA_SHADER_COMPUTE], sizeof(struct lvp_access_info));
570 state->dispatch_info.block[0] = pipeline->pipeline_nir[MESA_SHADER_COMPUTE]->info.workgroup_size[0];
571 state->dispatch_info.block[1] = pipeline->pipeline_nir[MESA_SHADER_COMPUTE]->info.workgroup_size[1];
572 state->dispatch_info.block[2] = pipeline->pipeline_nir[MESA_SHADER_COMPUTE]->info.workgroup_size[2];
573 state->inlines_dirty[PIPE_SHADER_COMPUTE] = pipeline->inlines[MESA_SHADER_COMPUTE].can_inline;
575 state->pctx->bind_compute_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_COMPUTE]);
579 set_viewport_depth_xform(struct rendering_state *state, unsigned idx)
581 double n = state->depth[idx].min;
582 double f = state->depth[idx].max;
584 if (!state->rs_state.clip_halfz) {
585 state->viewports[idx].scale[2] = 0.5 * (f - n);
586 state->viewports[idx].translate[2] = 0.5 * (n + f);
588 state->viewports[idx].scale[2] = (f - n);
589 state->viewports[idx].translate[2] = n;
594 get_viewport_xform(struct rendering_state *state,
603 state->viewports[idx].scale[0] = half_width;
604 state->viewports[idx].translate[0] = half_width + x;
605 state->viewports[idx].scale[1] = half_height;
606 state->viewports[idx].translate[1] = half_height + y;
608 memcpy(&state->depth[idx].min, &viewport->minDepth, sizeof(float) * 2);
612 struct rendering_state *state)
619 state->iv_dirty[sh] |= state->num_shader_images[sh] &&
620 (state->access[sh].images_read != pipeline->access[sh].images_read ||
621 state->access[sh].images_written != pipeline->access[sh].images_written);
622 state->sb_dirty[sh] |= state->num_shader_buffers[sh] && state->access[sh].buffers_written != pipeline->access[sh].buffers_written;
624 memcpy(state->access, pipeline->access, sizeof(struct lvp_access_info) * 5); //4 vertex stages + fragment
627 state->has_pcbuf[sh] = false;
631 state->uniform_blocks[sh].count = pipeline->layout->stage[i].uniform_block_count;
633 state->uniform_blocks[sh].size[j] = pipeline->layout->stage[i].uniform_block_sizes[j];
637 state->has_pcbuf[sh] = pipeline->layout->push_constant_size > 0;
638 if (!state->has_pcbuf[sh] && !state->uniform_blocks[sh].count)
639 state->pcbuf_dirty[sh] = false;
644 state->pctx->bind_gs_state(state->pctx, NULL);
645 if (state->pctx->bind_tcs_state)
646 state->pctx->bind_tcs_state(state->pctx, NULL);
647 if (state->pctx->bind_tes_state)
648 state->pctx->bind_tes_state(state->pctx, NULL);
649 state->gs_output_lines = GS_OUTPUT_NONE;
655 state->inlines_dirty[PIPE_SHADER_FRAGMENT] = pipeline->inlines[MESA_SHADER_FRAGMENT].can_inline;
657 state->pctx->bind_fs_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_FRAGMENT]);
661 state->inlines_dirty[PIPE_SHADER_VERTEX] = pipeline->inlines[MESA_SHADER_VERTEX].can_inline;
663 state->pctx->bind_vs_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_VERTEX]);
667 state->inlines_dirty[PIPE_SHADER_GEOMETRY] = pipeline->inlines[MESA_SHADER_GEOMETRY].can_inline;
669 state->pctx->bind_gs_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_GEOMETRY]);
670 state->gs_output_lines = pipeline->gs_output_lines ? GS_OUTPUT_LINES : GS_OUTPUT_NOT_LINES;
674 state->inlines_dirty[PIPE_SHADER_TESS_CTRL] = pipeline->inlines[MESA_SHADER_TESS_CTRL].can_inline;
676 state->pctx->bind_tcs_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_TESS_CTRL]);
680 state->inlines_dirty[PIPE_SHADER_TESS_EVAL] = pipeline->inlines[MESA_SHADER_TESS_EVAL].can_inline;
682 state->pctx->bind_tes_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_TESS_EVAL]);
694 state->pctx->bind_fs_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_FRAGMENT]);
695 if (state->pctx->bind_gs_state && !has_stage[PIPE_SHADER_GEOMETRY])
696 state->pctx->bind_gs_state(state->pctx, NULL);
697 if (state->pctx->bind_tcs_state && !has_stage[PIPE_SHADER_TESS_CTRL])
698 state->pctx->bind_tcs_state(state->pctx, NULL);
699 if (state->pctx->bind_tes_state && !has_stage[PIPE_SHADER_TESS_EVAL])
700 state->pctx->bind_tes_state(state->pctx, NULL);
702 /* rasterization state */
704 state->rs_state.depth_clamp = ps->rs->depth_clamp_enable;
705 state->rs_state.depth_clip_near = ps->rs->depth_clip_enable;
708 state->rs_state.rasterizer_discard = ps->rs->rasterizer_discard_enable;
710 state->rs_state.line_smooth = pipeline->line_smooth;
711 state->rs_state.line_stipple_enable = ps->rs->line.stipple.enable;
712 state->rs_state.fill_front = vk_polygon_mode_to_pipe(ps->rs->polygon_mode);
713 state->rs_state.fill_back = vk_polygon_mode_to_pipe(ps->rs->polygon_mode);
714 state->rs_state.point_size_per_vertex = true;
715 state->rs_state.flatshade_first =
717 state->rs_state.point_quad_rasterization = true;
718 state->rs_state.half_pixel_center = true;
719 state->rs_state.scissor = true;
720 state->rs_state.no_ms_sample_mask_out = true;
721 state->rs_state.line_rectangular = pipeline->line_rectangular;
724 state->rs_state.line_width = ps->rs->line.width;
726 state->rs_state.line_stipple_factor = ps->rs->line.stipple.factor - 1;
727 state->rs_state.line_stipple_pattern = ps->rs->line.stipple.pattern;
731 state->depth_bias.enabled = ps->rs->depth_bias.enable;
733 state->depth_bias.offset_units = ps->rs->depth_bias.constant;
734 state->depth_bias.offset_scale = ps->rs->depth_bias.slope;
735 state->depth_bias.offset_clamp = ps->rs->depth_bias.clamp;
739 state->rs_state.cull_face = vk_cull_to_pipe(ps->rs->cull_mode);
742 state->rs_state.front_ccw = (ps->rs->front_face == VK_FRONT_FACE_COUNTER_CLOCKWISE);
743 state->rs_dirty = true;
748 state->dsa_state.depth_enabled = ps->ds->depth.test_enable;
750 state->dsa_state.depth_writemask = ps->ds->depth.write_enable;
752 state->dsa_state.depth_func = ps->ds->depth.compare_op;
754 state->dsa_state.depth_bounds_test = ps->ds->depth.bounds_test.enable;
757 state->dsa_state.depth_bounds_min = ps->ds->depth.bounds_test.min;
758 state->dsa_state.depth_bounds_max = ps->ds->depth.bounds_test.max;
762 state->dsa_state.stencil[0].enabled = ps->ds->stencil.test_enable;
763 state->dsa_state.stencil[1].enabled = ps->ds->stencil.test_enable;
770 state->dsa_state.stencil[0].func = front->op.compare;
771 state->dsa_state.stencil[0].fail_op = vk_conv_stencil_op(front->op.fail);
772 state->dsa_state.stencil[0].zpass_op = vk_conv_stencil_op(front->op.pass);
773 state->dsa_state.stencil[0].zfail_op = vk_conv_stencil_op(front->op.depth_fail);
775 state->dsa_state.stencil[1].func = back->op.compare;
776 state->dsa_state.stencil[1].fail_op = vk_conv_stencil_op(back->op.fail);
777 state->dsa_state.stencil[1].zpass_op = vk_conv_stencil_op(back->op.pass);
778 state->dsa_state.stencil[1].zfail_op = vk_conv_stencil_op(back->op.depth_fail);
782 state->dsa_state.stencil[0].valuemask = front->compare_mask;
783 state->dsa_state.stencil[1].valuemask = back->compare_mask;
787 state->dsa_state.stencil[0].writemask = front->write_mask;
788 state->dsa_state.stencil[1].writemask = back->write_mask;
792 state->stencil_ref.ref_value[0] = front->reference;
793 state->stencil_ref.ref_value[1] = back->reference;
794 state->stencil_ref_dirty = true;
796 state->dsa_dirty = true;
800 state->blend_state.logicop_enable = ps->cb->logic_op_enable;
803 state->blend_state.logicop_func = vk_conv_logic_op(ps->cb->logic_op);
807 state->color_write_disables = ~ps->cb->color_write_enables;
809 state->blend_state.independent_blend_enable = (ps->cb->attachment_count > 1);
813 state->blend_state.rt[i].colormask = att->write_mask;
814 state->blend_state.rt[i].blend_enable = att->blend_enable;
816 state->blend_state.rt[i].rgb_func = vk_conv_blend_func(att->color_blend_op);
817 state->blend_state.rt[i].rgb_src_factor = vk_conv_blend_factor(att->src_color_blend_factor);
818 state->blend_state.rt[i].rgb_dst_factor = vk_conv_blend_factor(att->dst_color_blend_factor);
819 state->blend_state.rt[i].alpha_func = vk_conv_blend_func(att->alpha_blend_op);
820 state->blend_state.rt[i].alpha_src_factor = vk_conv_blend_factor(att->src_alpha_blend_factor);
821 state->blend_state.rt[i].alpha_dst_factor = vk_conv_blend_factor(att->dst_alpha_blend_factor);
823 state->blend_state.rt[i].rgb_func = 0;
824 state->blend_state.rt[i].rgb_src_factor = 0;
825 state->blend_state.rt[i].rgb_dst_factor = 0;
826 state->blend_state.rt[i].alpha_func = 0;
827 state->blend_state.rt[i].alpha_src_factor = 0;
828 state->blend_state.rt[i].alpha_dst_factor = 0;
837 state->blend_state.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ONE;
838 state->blend_state.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ONE;
843 state->blend_state.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ONE;
844 state->blend_state.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ONE;
847 state->blend_dirty = true;
849 memcpy(state->blend_color.color, ps->cb->blend_constants, 4 * sizeof(float));
850 state->blend_color_dirty = true;
853 memset(&state->blend_state, 0, sizeof(state->blend_state));
854 state->blend_dirty = true;
857 state->disable_multisample = pipeline->disable_multisample;
859 state->rs_state.multisample = ps->ms->rasterization_samples > 1;
860 state->sample_mask = ps->ms->sample_mask;
861 state->blend_state.alpha_to_coverage = ps->ms->alpha_to_coverage_enable;
862 state->blend_state.alpha_to_one = ps->ms->alpha_to_one_enable;
863 state->blend_dirty = true;
864 state->rs_dirty = true;
865 state->min_samples = 1;
866 state->sample_mask_dirty = true;
869 state->min_samples = ceil(ps->ms->rasterization_samples *
871 if (state->min_samples > 1)
872 state->min_samples = ps->ms->rasterization_samples;
873 if (state->min_samples < 1)
874 state->min_samples = 1;
877 state->min_samples = ps->ms->rasterization_samples;
878 state->min_samples_dirty = true;
880 state->rs_state.multisample = false;
881 state->sample_mask_dirty = state->sample_mask != 0xffffffff;
882 state->sample_mask = 0xffffffff;
883 state->min_samples_dirty = state->min_samples;
884 state->min_samples = 0;
885 state->blend_dirty |= state->blend_state.alpha_to_coverage || state->blend_state.alpha_to_one;
886 state->blend_state.alpha_to_coverage = false;
887 state->blend_state.alpha_to_one = false;
888 state->rs_dirty = true;
893 state->vb[b].stride = ps->vi->bindings[b].stride;
894 state->vb_dirty = true;
900 state->velem.velems[a].src_offset = ps->vi->attributes[a].offset;
901 state->velem.velems[a].vertex_buffer_index = b;
902 state->velem.velems[a].src_format =
904 state->velem.velems[a].dual_slot = false;
909 state->velem.velems[a].instance_divisor = 0;
912 state->velem.velems[a].instance_divisor = d ? d : UINT32_MAX;
919 state->velem.count = util_last_bit(ps->vi->attributes_valid);
920 state->vb_dirty = true;
921 state->ve_dirty = true;
925 state->info.mode = vk_conv_topology(ps->ia->primitive_topology);
926 state->rs_dirty = true;
929 state->info.primitive_restart = ps->ia->primitive_restart_enable;
932 state->patch_vertices = ps->ts->patch_control_points;
936 state->num_viewports = ps->vp->viewport_count;
937 state->vp_dirty = true;
940 state->num_scissors = ps->vp->scissor_count;
941 state->scissor_dirty = true;
946 get_viewport_xform(state, &ps->vp->viewports[i], i);
947 set_viewport_depth_xform(state, i);
949 state->vp_dirty = true;
954 state->scissors[i].minx = ss->offset.x;
955 state->scissors[i].miny = ss->offset.y;
956 state->scissors[i].maxx = ss->offset.x + ss->extent.width;
957 state->scissors[i].maxy = ss->offset.y + ss->extent.height;
959 state->scissor_dirty = true;
962 if (state->rs_state.clip_halfz != !ps->vp->negative_one_to_one) {
963 state->rs_state.clip_halfz = !ps->vp->negative_one_to_one;
964 state->rs_dirty = true;
965 for (uint32_t i = 0; i < state->num_viewports; i++)
966 set_viewport_depth_xform(state, i);
967 state->vp_dirty = true;
971 if (fb_samples != state->framebuffer.samples) {
972 state->framebuffer.samples = fb_samples;
973 state->pctx->set_framebuffer_state(state->pctx, &state->framebuffer);
978 handle_pipeline_access(struct rendering_state *state, gl_shader_stage stage)
982 state->iv[pstage][i].access = 0;
983 state->iv[pstage][i].shader_access = 0;
985 u_foreach_bit(idx, state->access[stage].images_read) {
986 state->iv[pstage][idx].access |= PIPE_IMAGE_ACCESS_READ;
987 state->iv[pstage][idx].shader_access |= PIPE_IMAGE_ACCESS_READ;
989 u_foreach_bit(idx, state->access[stage].images_written) {
990 state->iv[pstage][idx].access |= PIPE_IMAGE_ACCESS_WRITE;
991 state->iv[pstage][idx].shader_access |= PIPE_IMAGE_ACCESS_WRITE;
996 struct rendering_state *state)
1000 handle_compute_pipeline(cmd, state);
1001 handle_pipeline_access(state, MESA_SHADER_COMPUTE);
1003 handle_graphics_pipeline(cmd, state);
1005 handle_pipeline_access(state, i);
1007 state->push_size[pipeline->is_compute_pipeline] = pipeline->layout->push_constant_size;
1008 state->pipeline[pipeline->is_compute_pipeline] = pipeline;
1012 struct rendering_state *state)
1020 state->vb[idx].buffer_offset = vcb->offsets[i];
1021 state->vb[idx].buffer.resource =
1025 state->vb[idx].stride = vcb->strides[i];
1027 if (vcb->first_binding < state->start_vb)
1028 state->start_vb = vcb->first_binding;
1029 if (vcb->first_binding + vcb->binding_count >= state->num_vb)
1030 state->num_vb = vcb->first_binding + vcb->binding_count;
1031 state->vb_dirty = true;
1074 static void fill_sampler_stage(struct rendering_state *state,
1087 fill_sampler(&state->ss[p_stage][ss_idx], binding->immutable_samplers ? binding->immutable_samplers[array_idx] : descriptor->sampler);
1088 if (state->num_sampler_states[p_stage] <= ss_idx)
1089 state->num_sampler_states[p_stage] = ss_idx + 1;
1090 state->ss_dirty[p_stage] = true;
1102 static void fill_sampler_view_stage(struct rendering_state *state,
1160 assert(sv_idx < ARRAY_SIZE(state->sv[p_stage]));
1161 if (state->sv[p_stage][sv_idx])
1162 pipe_sampler_view_reference(&state->sv[p_stage][sv_idx], NULL);
1163 state->sv[p_stage][sv_idx] = state->pctx->create_sampler_view(state->pctx, iv->image->bo, &templ);
1165 state->sv[p_stage][sv_idx] = NULL;
1167 if (state->num_sampler_views[p_stage] <= sv_idx)
1168 state->num_sampler_views[p_stage] = sv_idx + 1;
1169 state->sv_dirty[p_stage] = true;
1172 static void fill_sampler_buffer_view_stage(struct rendering_state *state,
1187 assert(sv_idx < ARRAY_SIZE(state->sv[p_stage]));
1188 if (state->sv[p_stage][sv_idx])
1189 pipe_sampler_view_reference(&state->sv[p_stage][sv_idx], NULL);
1203 templ.context = state->pctx;
1204 state->sv[p_stage][sv_idx] = state->pctx->create_sampler_view(state->pctx, bv->buffer->bo, &templ);
1207 if (state->num_sampler_views[p_stage] <= sv_idx)
1208 state->num_sampler_views[p_stage] = sv_idx + 1;
1209 state->sv_dirty[p_stage] = true;
1212 static void fill_image_view_stage(struct rendering_state *state,
1227 state->iv[p_stage][idx].resource = iv->image->bo;
1229 state->iv[p_stage][idx].format = lvp_vk_format_to_pipe_format(iv->vk.format);
1231 state->iv[p_stage][idx].format = util_format_stencil_only(lvp_vk_format_to_pipe_format(iv->vk.format));
1233 state->iv[p_stage][idx].format = lvp_vk_format_to_pipe_format(iv->vk.format);
1236 state->iv[p_stage][idx].u.tex.first_layer = 0;
1237 state->iv[p_stage][idx].u.tex.last_layer = iv->vk.extent.depth - 1;
1239 state->iv[p_stage][idx].u.tex.first_layer = iv->vk.base_array_layer,
1240 state->iv[p_stage][idx].u.tex.last_layer = iv->vk.base_array_layer + iv->vk.layer_count - 1;
1242 state->iv[p_stage][idx].u.tex.level = iv->vk.base_mip_level;
1244 state->iv[p_stage][idx].resource = NULL;
1245 state->iv[p_stage][idx].format = PIPE_FORMAT_NONE;
1246 state->iv[p_stage][idx].u.tex.first_layer = 0;
1247 state->iv[p_stage][idx].u.tex.last_layer = 0;
1248 state->iv[p_stage][idx].u.tex.level = 0;
1251 if (state->num_shader_images[p_stage] <= idx)
1252 state->num_shader_images[p_stage] = idx + 1;
1254 state->iv_dirty[p_stage] = true;
1257 static void fill_image_buffer_view_stage(struct rendering_state *state,
1272 state->iv[p_stage][idx].resource = bv->buffer->bo;
1273 state->iv[p_stage][idx].format = bv->pformat;
1274 state->iv[p_stage][idx].u.buf.offset = bv->offset + bv->buffer->offset;
1275 state->iv[p_stage][idx].u.buf.size = bv->range == VK_WHOLE_SIZE ? (bv->buffer->size - bv->offset): bv->range;
1277 state->iv[p_stage][idx].resource = NULL;
1278 state->iv[p_stage][idx].format = PIPE_FORMAT_NONE;
1279 state->iv[p_stage][idx].u.buf.offset = 0;
1280 state->iv[p_stage][idx].u.buf.size = 0;
1282 if (state->num_shader_images[p_stage] <= idx)
1283 state->num_shader_images[p_stage] = idx + 1;
1284 state->iv_dirty[p_stage] = true;
1287 static void handle_descriptor(struct rendering_state *state,
1306 state->uniform_blocks[p_stage].block[idx] = descriptor->uniform;
1307 state->pcbuf_dirty[p_stage] = true;
1308 state->inlines_dirty[p_stage] = true;
1313 fill_image_view_stage(state, dyn_info, stage, p_stage, array_idx, descriptor, binding);
1324 state->const_buffer[p_stage][idx].buffer = NULL;
1325 state->const_buffer[p_stage][idx].buffer_offset = 0;
1326 state->const_buffer[p_stage][idx].buffer_size = 0;
1328 state->const_buffer[p_stage][idx].buffer = descriptor->buffer->bo;
1329 state->const_buffer[p_stage][idx].buffer_offset = descriptor->offset + descriptor->buffer->offset;
1331 state->const_buffer[p_stage][idx].buffer_size = descriptor->buffer->bo->width0 - state->const_buffer[p_stage][idx].buffer_offset;
1333 state->const_buffer[p_stage][idx].buffer_size = descriptor->range;
1337 state->const_buffer[p_stage][idx].buffer_offset += offset;
1339 if (state->num_const_bufs[p_stage] <= idx)
1340 state->num_const_bufs[p_stage] = idx + 1;
1341 state->constbuf_dirty[p_stage] = true;
1342 state->inlines_dirty[p_stage] = true;
1353 state->sb[p_stage][idx].buffer = NULL;
1354 state->sb[p_stage][idx].buffer_offset = 0;
1355 state->sb[p_stage][idx].buffer_size = 0;
1357 state->sb[p_stage][idx].buffer = descriptor->buffer->bo;
1358 state->sb[p_stage][idx].buffer_offset = descriptor->offset + descriptor->buffer->offset;
1360 state->sb[p_stage][idx].buffer_size = descriptor->buffer->bo->width0 - state->sb[p_stage][idx].buffer_offset;
1362 state->sb[p_stage][idx].buffer_size = descriptor->range;
1366 state->sb[p_stage][idx].buffer_offset += offset;
1368 if (state->num_shader_buffers[p_stage] <= idx)
1369 state->num_shader_buffers[p_stage] = idx + 1;
1370 state->sb_dirty[p_stage] = true;
1376 fill_sampler_stage(state, dyn_info, stage, p_stage, array_idx, descriptor, binding);
1379 fill_sampler_view_stage(state, dyn_info, stage, p_stage, array_idx, descriptor, binding);
1382 fill_sampler_stage(state, dyn_info, stage, p_stage, array_idx, descriptor, binding);
1383 fill_sampler_view_stage(state, dyn_info, stage, p_stage, array_idx, descriptor, binding);
1386 fill_sampler_buffer_view_stage(state, dyn_info, stage, p_stage, array_idx, descriptor, binding);
1389 fill_image_buffer_view_stage(state, dyn_info, stage, p_stage, array_idx, descriptor, binding);
1398 static void handle_set_stage(struct rendering_state *state,
1414 handle_descriptor(state, dyn_info, binding, stage, p_stage, i, descriptor->type, &descriptor->info);
1441 struct rendering_state *state)
1454 handle_set_stage(state, dyn_info, set, MESA_SHADER_COMPUTE, PIPE_SHADER_COMPUTE);
1460 struct rendering_state *state)
1473 handle_compute_descriptor_sets(cmd, &dyn_info, state);
1496 handle_set_stage(state, &dyn_info, set, MESA_SHADER_VERTEX, PIPE_SHADER_VERTEX);
1499 handle_set_stage(state, &dyn_info, set, MESA_SHADER_GEOMETRY, PIPE_SHADER_GEOMETRY);
1502 handle_set_stage(state, &dyn_info, set, MESA_SHADER_TESS_CTRL, PIPE_SHADER_TESS_CTRL);
1505 handle_set_stage(state, &dyn_info, set, MESA_SHADER_TESS_EVAL, PIPE_SHADER_TESS_EVAL);
1508 handle_set_stage(state, &dyn_info, set, MESA_SHADER_FRAGMENT, PIPE_SHADER_FRAGMENT);
1514 static struct pipe_surface *create_img_surface_bo(struct rendering_state *state,
1536 return state->pctx->create_surface(state->pctx,
1540 static struct pipe_surface *create_img_surface(struct rendering_state *state,
1549 return create_img_surface_bo(state, &imgv_subres, imgv->image->bo,
1554 static void add_img_view_surface(struct rendering_state *state,
1566 imgv->surface = create_img_surface(state, imgv, imgv->vk.format,
1573 render_needs_clear(struct rendering_state *state)
1575 for (uint32_t i = 0; i < state->color_att_count; i++) {
1576 if (state->color_att[i].load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
1579 if (state->depth_att.load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
1581 if (state->stencil_att.load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
1586 static void clear_attachment_layers(struct rendering_state *state,
1594 struct pipe_surface *clear_surf = create_img_surface(state,
1597 state->framebuffer.width,
1598 state->framebuffer.height,
1603 state->pctx->clear_depth_stencil(state->pctx,
1611 state->pctx->clear_render_target(state->pctx, clear_surf,
1617 state->pctx->surface_destroy(state->pctx, clear_surf);
1620 static void render_clear(struct rendering_state *state)
1622 for (uint32_t i = 0; i < state->color_att_count; i++) {
1623 if (state->color_att[i].load_op != VK_ATTACHMENT_LOAD_OP_CLEAR)
1627 const VkClearValue value = state->color_att[i].clear_value;
1633 struct lvp_image_view *imgv = state->color_att[i].imgv;
1636 if (state->info.view_mask) {
1637 u_foreach_bit(i, state->info.view_mask)
1638 clear_attachment_layers(state, imgv, &state->render_area,
1641 state->pctx->clear_render_target(state->pctx,
1644 state->render_area.offset.x,
1645 state->render_area.offset.y,
1646 state->render_area.extent.width,
1647 state->render_area.extent.height,
1654 if (state->depth_att.load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1656 dclear_val = state->depth_att.clear_value.depthStencil.depth;
1660 if (state->stencil_att.load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1662 sclear_val = state->stencil_att.clear_value.depthStencil.stencil;
1666 if (state->info.view_mask) {
1667 u_foreach_bit(i, state->info.view_mask)
1668 clear_attachment_layers(state, state->ds_imgv, &state->render_area,
1671 state->pctx->clear_depth_stencil(state->pctx,
1672 state->ds_imgv->surface,
1675 state->render_area.offset.x,
1676 state->render_area.offset.y,
1677 state->render_area.extent.width,
1678 state->render_area.extent.height,
1684 static void render_clear_fast(struct rendering_state *state)
1687 * the state tracker clear interface only works if all the attachments have the same
1691 if (state->render_area.offset.x || state->render_area.offset.y)
1694 if (state->render_area.extent.width != state->framebuffer.width ||
1695 state->render_area.extent.height != state->framebuffer.height)
1698 if (state->info.view_mask)
1704 for (uint32_t i = 0; i < state->color_att_count; i++) {
1705 if (state->color_att[i].load_op != VK_ATTACHMENT_LOAD_OP_CLEAR)
1711 if (memcmp(&color_value, &state->color_att[i].clear_value, sizeof(VkClearValue)))
1714 memcpy(&color_value, &state->color_att[i].clear_value, sizeof(VkClearValue));
1720 if (state->depth_att.load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1722 dclear_val = state->depth_att.clear_value.depthStencil.depth;
1726 if (state->stencil_att.load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1728 sclear_val = state->stencil_att.clear_value.depthStencil.stencil;
1735 state->pctx->clear(state->pctx, buffers,
1741 render_clear(state);
1745 destroy_multisample_surface(struct rendering_state *state, struct lvp_image_view *imgv)
1757 resolve_ds(struct rendering_state *state, bool multi)
1759 VkResolveModeFlagBits depth_resolve_mode = multi ? state->forced_depth_resolve_mode : state->depth_att.resolve_mode;
1760 VkResolveModeFlagBits stencil_resolve_mode = multi ? state->forced_stencil_resolve_mode : state->stencil_att.resolve_mode;
1764 struct lvp_image_view *src_imgv = state->ds_imgv;
1770 assert(state->depth_att.resolve_imgv == NULL ||
1771 state->stencil_att.resolve_imgv == NULL ||
1772 state->depth_att.resolve_imgv == state->stencil_att.resolve_imgv ||
1776 state->depth_att.resolve_imgv ? state->depth_att.resolve_imgv :
1777 state->stencil_att.resolve_imgv;
1811 info.src.box.x = state->render_area.offset.x;
1812 info.src.box.y = state->render_area.offset.y;
1813 info.src.box.width = state->render_area.extent.width;
1814 info.src.box.height = state->render_area.extent.height;
1815 info.src.box.depth = state->framebuffer.layers;
1819 state->pctx->blit(state->pctx, &info);
1822 state->ds_imgv = destroy_multisample_surface(state, state->ds_imgv);
1826 resolve_color(struct rendering_state *state, bool multi)
1828 for (uint32_t i = 0; i < state->color_att_count; i++) {
1829 if (!state->color_att[i].resolve_mode &&
1830 !(multi && state->forced_sample_count && state->color_att[i].imgv))
1833 struct lvp_image_view *src_imgv = state->color_att[i].imgv;
1837 struct lvp_image_view *dst_imgv = multi ? src_imgv->multisample : state->color_att[i].resolve_imgv;
1848 info.src.box.x = state->render_area.offset.x;
1849 info.src.box.y = state->render_area.offset.y;
1850 info.src.box.width = state->render_area.extent.width;
1851 info.src.box.height = state->render_area.extent.height;
1852 info.src.box.depth = state->framebuffer.layers;
1859 state->pctx->blit(state->pctx, &info);
1864 for (uint32_t i = 0; i < state->color_att_count; i++) {
1865 struct lvp_image_view *src_imgv = state->color_att[i].imgv;
1867 state->color_att[i].imgv = destroy_multisample_surface(state, src_imgv);
1871 static void render_resolve(struct rendering_state *state)
1873 if (state->forced_sample_count) {
1874 resolve_ds(state, true);
1875 resolve_color(state, true);
1877 resolve_ds(state, false);
1878 resolve_color(state, false);
1882 replicate_attachment(struct rendering_state *state, struct lvp_image_view *src, struct lvp_image_view *dst)
1891 state->pctx->resource_copy_region(state->pctx, dst->image->bo, level, 0, 0, 0, src->image->bo, level, &box);
1895 create_multisample_surface(struct rendering_state *state, struct lvp_image_view *imgv, uint32_t samples, bool replicate)
1904 image->bo = state->pctx->screen->resource_create(state->pctx->screen, &templ);
1908 multi->surface = state->pctx->create_surface(state->pctx, image->bo, imgv->surface);
1914 replicate_attachment(state, imgv, multi);
1919 att_needs_replicate(const struct rendering_state *state, const struct lvp_image_view *imgv, VkAttachmentLoadOp load_op)
1923 if (state->render_area.offset.x || state->render_area.offset.y)
1925 if (state->render_area.extent.width < imgv->image->vk.extent.width ||
1926 state->render_area.extent.height < imgv->image->vk.extent.height)
1954 struct rendering_state *state)
1963 state->forced_sample_count = ssi->rasterizationSamples;
1964 state->forced_depth_resolve_mode = info->pDepthAttachment ? info->pDepthAttachment->resolveMode : 0;
1965 state->forced_stencil_resolve_mode = info->pStencilAttachment ? info->pStencilAttachment->resolveMode : 0;
1967 state->forced_sample_count = 0;
1968 state->forced_depth_resolve_mode = 0;
1969 state->forced_stencil_resolve_mode = 0;
1972 state->info.view_mask = info->viewMask;
1973 state->render_area = info->renderArea;
1974 state->suspending = suspending;
1975 state->framebuffer.width = info->renderArea.offset.x +
1977 state->framebuffer.height = info->renderArea.offset.y +
1979 state->framebuffer.layers = info->viewMask ? util_last_bit(info->viewMask) : info->layerCount;
1980 state->framebuffer.nr_cbufs = info->colorAttachmentCount;
1982 state->color_att_count = info->colorAttachmentCount;
1983 state->color_att = realloc(state->color_att, sizeof(*state->color_att) * state->color_att_count);
1985 render_att_init(&state->color_att[i], &info->pColorAttachments[i]);
1986 if (state->color_att[i].imgv) {
1987 struct lvp_image_view *imgv = state->color_att[i].imgv;
1988 add_img_view_surface(state, imgv,
1989 state->framebuffer.width, state->framebuffer.height,
1990 state->framebuffer.layers);
1991 if (state->forced_sample_count && imgv->image->vk.samples == 1)
1992 state->color_att[i].imgv = create_multisample_surface(state, imgv, state->forced_sample_count,
1993 att_needs_replicate(state, imgv, state->color_att[i].load_op));
1994 state->framebuffer.cbufs[i] = state->color_att[i].imgv->surface;
1996 state->framebuffer.cbufs[i] = NULL;
2000 render_att_init(&state->depth_att, info->pDepthAttachment);
2001 render_att_init(&state->stencil_att, info->pStencilAttachment);
2002 if (state->depth_att.imgv || state->stencil_att.imgv) {
2003 assert(state->depth_att.imgv == NULL ||
2004 state->stencil_att.imgv == NULL ||
2005 state->depth_att.imgv == state->stencil_att.imgv);
2006 state->ds_imgv = state->depth_att.imgv ? state->depth_att.imgv :
2007 state->stencil_att.imgv;
2008 struct lvp_image_view *imgv = state->ds_imgv;
2009 add_img_view_surface(state, imgv,
2010 state->framebuffer.width, state->framebuffer.height,
2011 state->framebuffer.layers);
2012 if (state->forced_sample_count && imgv->image->vk.samples == 1) {
2014 if (state->depth_att.load_op == VK_ATTACHMENT_LOAD_OP_CLEAR ||
2015 state->stencil_att.load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
2017 else if (state->depth_att.load_op == VK_ATTACHMENT_LOAD_OP_LOAD ||
2018 state->stencil_att.load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
2022 state->ds_imgv = create_multisample_surface(state, imgv, state->forced_sample_count,
2023 att_needs_replicate(state, imgv, load_op));
2025 state->framebuffer.zsbuf = state->ds_imgv->surface;
2027 state->ds_imgv = NULL;
2028 state->framebuffer.zsbuf = NULL;
2031 state->pctx->set_framebuffer_state(state->pctx,
2032 &state->framebuffer);
2034 if (!resuming && render_needs_clear(state))
2035 render_clear_fast(state);
2039 struct rendering_state *state)
2041 if (!state->suspending)
2042 render_resolve(state);
2046 struct rendering_state *state)
2050 state->info.index_size = 0;
2051 state->info.index.resource = NULL;
2052 state->info.start_instance = cmd->u.draw.first_instance;
2053 state->info.instance_count = cmd->u.draw.instance_count;
2058 state->pctx->set_patch_vertices(state->pctx, state->patch_vertices);
2059 state->pctx->draw_vbo(state->pctx, &state->info, 0, NULL, &draw, 1);
2063 struct rendering_state *state)
2068 state->info.index_size = 0;
2069 state->info.index.resource = NULL;
2070 state->info.start_instance = cmd->u.draw_multi_ext.first_instance;
2071 state->info.instance_count = cmd->u.draw_multi_ext.instance_count;
2073 state->info.increment_draw_id = true;
2081 state->pctx->set_patch_vertices(state->pctx, state->patch_vertices);
2084 state->pctx->draw_vbo(state->pctx, &state->info, 0, NULL, draws, cmd->u.draw_multi_ext.draw_count);
2091 struct rendering_state *state)
2096 state->num_viewports = viewport_count;
2103 get_viewport_xform(state, vp, idx);
2104 set_viewport_depth_xform(state, idx);
2106 state->vp_dirty = true;
2110 struct rendering_state *state)
2115 state);
2119 struct rendering_state *state)
2124 state);
2130 struct rendering_state *state)
2135 state->num_scissors = scissor_count;
2142 state->scissors[idx].minx = ss->offset.x;
2143 state->scissors[idx].miny = ss->offset.y;
2144 state->scissors[idx].maxx = ss->offset.x + ss->extent.width;
2145 state->scissors[idx].maxy = ss->offset.y + ss->extent.height;
2147 state->scissor_dirty = true;
2151 struct rendering_state *state)
2156 state);
2160 struct rendering_state *state)
2165 state);
2169 struct rendering_state *state)
2171 state->rs_state.line_width = cmd->u.set_line_width.line_width;
2172 state->rs_dirty = true;
2176 struct rendering_state *state)
2178 state->depth_bias.offset_units = cmd->u.set_depth_bias.depth_bias_constant_factor;
2179 state->depth_bias.offset_scale = cmd->u.set_depth_bias.depth_bias_slope_factor;
2180 state->depth_bias.offset_clamp = cmd->u.set_depth_bias.depth_bias_clamp;
2181 state->rs_dirty = true;
2185 struct rendering_state *state)
2187 memcpy(state->blend_color.color, cmd->u.set_blend_constants.blend_constants, 4 * sizeof(float));
2188 state->blend_color_dirty = true;
2192 struct rendering_state *state)
2194 state->dsa_dirty |= !DOUBLE_EQ(state->dsa_state.depth_bounds_min, cmd->u.set_depth_bounds.min_depth_bounds);
2195 state->dsa_dirty |= !DOUBLE_EQ(state->dsa_state.depth_bounds_max, cmd->u.set_depth_bounds.max_depth_bounds);
2196 state->dsa_state.depth_bounds_min = cmd->u.set_depth_bounds.min_depth_bounds;
2197 state->dsa_state.depth_bounds_max = cmd->u.set_depth_bounds.max_depth_bounds;
2201 struct rendering_state *state)
2204 state->dsa_state.stencil[0].valuemask = cmd->u.set_stencil_compare_mask.compare_mask;
2206 state->dsa_state.stencil[1].valuemask = cmd->u.set_stencil_compare_mask.compare_mask;
2207 state->dsa_dirty = true;
2211 struct rendering_state *state)
2214 state->dsa_state.stencil[0].writemask = cmd->u.set_stencil_write_mask.write_mask;
2216 state->dsa_state.stencil[1].writemask = cmd->u.set_stencil_write_mask.write_mask;
2217 state->dsa_dirty = true;
2221 struct rendering_state *state)
2224 state->stencil_ref.ref_value[0] = cmd->u.set_stencil_reference.reference;
2226 state->stencil_ref.ref_value[1] = cmd->u.set_stencil_reference.reference;
2227 state->stencil_ref_dirty = true;
2341 struct rendering_state *state)
2359 src_data = state->pctx->texture_map(state->pctx,
2372 dst_data = state->pctx->buffer_map(state->pctx,
2410 state->pctx->texture_unmap(state->pctx, src_t);
2411 state->pctx->buffer_unmap(state->pctx, dst_t);
2416 struct rendering_state *state)
2433 src_data = state->pctx->buffer_map(state->pctx,
2448 dst_data = state->pctx->texture_map(state->pctx,
2490 state->pctx->buffer_unmap(state->pctx, src_t);
2491 state->pctx->texture_unmap(state->pctx, dst_t);
2496 struct rendering_state *state)
2520 state->pctx->resource_copy_region(state->pctx, dst_image->bo,
2532 struct rendering_state *state)
2540 state->pctx->resource_copy_region(state->pctx, lvp_buffer_from_handle(copycmd->dstBuffer)->bo, 0,
2547 struct rendering_state *state)
2628 state->pctx->blit(state->pctx, &info);
2633 struct rendering_state *state)
2643 state->pctx->clear_buffer(state->pctx,
2652 struct rendering_state *state)
2660 dst = state->pctx->buffer_map(state->pctx,
2668 state->pctx->buffer_unmap(state->pctx, dst_t);
2672 struct rendering_state *state)
2676 state->info.index_bounds_valid = false;
2677 state->info.min_index = 0;
2678 state->info.max_index = ~0;
2679 state->info.index_size = state->index_size;
2680 state->info.index.resource = state->index_buffer;
2681 state->info.start_instance = cmd->u.draw_indexed.first_instance;
2682 state->info.instance_count = cmd->u.draw_indexed.instance_count;
2684 if (state->info.primitive_restart)
2685 state->info.restart_index = util_prim_restart_index_from_size(state->info.index_size);
2690 draw.start = (state->index_offset / state->index_size) + cmd->u.draw_indexed.first_index;
2692 state->info.index_bias_varies = !cmd->u.draw_indexed.vertex_offset;
2693 state->pctx->set_patch_vertices(state->pctx, state->patch_vertices);
2694 state->pctx->draw_vbo(state->pctx, &state->info, 0, NULL, &draw, 1);
2698 struct rendering_state *state)
2703 state->info.index_bounds_valid = false;
2704 state->info.min_index = 0;
2705 state->info.max_index = ~0;
2706 state->info.index_size = state->index_size;
2707 state->info.index.resource = state->index_buffer;
2708 state->info.start_instance = cmd->u.draw_multi_indexed_ext.first_instance;
2709 state->info.instance_count = cmd->u.draw_multi_indexed_ext.instance_count;
2711 state->info.increment_draw_id = true;
2713 if (state->info.primitive_restart)
2714 state->info.restart_index = util_prim_restart_index_from_size(state->info.index_size);
2726 draws[i].start = (state->index_offset / state->index_size) + draws[i].start;
2728 state->info.index_bias_varies = !cmd->u.draw_multi_indexed_ext.vertex_offset;
2729 state->pctx->set_patch_vertices(state->pctx, state->patch_vertices);
2732 state->pctx->draw_vbo(state->pctx, &state->info, 0, NULL, draws, cmd->u.draw_multi_indexed_ext.draw_count);
2738 struct rendering_state *state, bool indexed)
2742 state->info.index_bounds_valid = false;
2743 state->info.index_size = state->index_size;
2744 state->info.index.resource = state->index_buffer;
2745 state->info.max_index = ~0;
2746 if (state->info.primitive_restart)
2747 state->info.restart_index = util_prim_restart_index_from_size(state->info.index_size);
2749 state->info.index_size = 0;
2750 state->indirect_info.offset = cmd->u.draw_indirect.offset;
2751 state->indirect_info.stride = cmd->u.draw_indirect.stride;
2752 state->indirect_info.draw_count = cmd->u.draw_indirect.draw_count;
2753 state->indirect_info.buffer = lvp_buffer_from_handle(cmd->u.draw_indirect.buffer)->bo;
2755 state->pctx->set_patch_vertices(state->pctx, state->patch_vertices);
2756 state->pctx->draw_vbo(state->pctx, &state->info, 0, &state->indirect_info, &draw, 1);
2760 struct rendering_state *state)
2765 state->index_size = 1;
2768 state->index_size = 2;
2771 state->index_size = 4;
2776 state->index_offset = ib->offset;
2778 state->index_buffer = lvp_buffer_from_handle(ib->buffer)->bo;
2780 state->index_buffer = NULL;
2782 state->ib_dirty = true;
2786 struct rendering_state *state)
2788 state->dispatch_info.grid[0] = cmd->u.dispatch.group_count_x;
2789 state->dispatch_info.grid[1] = cmd->u.dispatch.group_count_y;
2790 state->dispatch_info.grid[2] = cmd->u.dispatch.group_count_z;
2791 state->dispatch_info.grid_base[0] = 0;
2792 state->dispatch_info.grid_base[1] = 0;
2793 state->dispatch_info.grid_base[2] = 0;
2794 state->dispatch_info.indirect = NULL;
2795 state->pctx->launch_grid(state->pctx, &state->dispatch_info);
2799 struct rendering_state *state)
2801 state->dispatch_info.grid[0] = cmd->u.dispatch_base.group_count_x;
2802 state->dispatch_info.grid[1] = cmd->u.dispatch_base.group_count_y;
2803 state->dispatch_info.grid[2] = cmd->u.dispatch_base.group_count_z;
2804 state->dispatch_info.grid_base[0] = cmd->u.dispatch_base.base_group_x;
2805 state->dispatch_info.grid_base[1] = cmd->u.dispatch_base.base_group_y;
2806 state->dispatch_info.grid_base[2] = cmd->u.dispatch_base.base_group_z;
2807 state->dispatch_info.indirect = NULL;
2808 state->pctx->launch_grid(state->pctx, &state->dispatch_info);
2812 struct rendering_state *state)
2814 state->dispatch_info.indirect = lvp_buffer_from_handle(cmd->u.dispatch_indirect.buffer)->bo;
2815 state->dispatch_info.indirect_offset = cmd->u.dispatch_indirect.offset;
2816 state->pctx->launch_grid(state->pctx, &state->dispatch_info);
2820 struct rendering_state *state)
2822 memcpy(state->push_constants + cmd->u.push_constants.offset, cmd->u.push_constants.values, cmd->u.push_constants.size);
2825 state->pcbuf_dirty[PIPE_SHADER_VERTEX] |= (stage_flags & VK_SHADER_STAGE_VERTEX_BIT) > 0;
2826 state->pcbuf_dirty[PIPE_SHADER_FRAGMENT] |= (stage_flags & VK_SHADER_STAGE_FRAGMENT_BIT) > 0;
2827 state->pcbuf_dirty[PIPE_SHADER_GEOMETRY] |= (stage_flags & VK_SHADER_STAGE_GEOMETRY_BIT) > 0;
2828 state->pcbuf_dirty[PIPE_SHADER_TESS_CTRL] |= (stage_flags & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) > 0;
2829 state->pcbuf_dirty[PIPE_SHADER_TESS_EVAL] |= (stage_flags & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) > 0;
2830 state->pcbuf_dirty[PIPE_SHADER_COMPUTE] |= (stage_flags & VK_SHADER_STAGE_COMPUTE_BIT) > 0;
2831 state->inlines_dirty[PIPE_SHADER_VERTEX] |= (stage_flags & VK_SHADER_STAGE_VERTEX_BIT) > 0;
2832 state->inlines_dirty[PIPE_SHADER_FRAGMENT] |= (stage_flags & VK_SHADER_STAGE_FRAGMENT_BIT) > 0;
2833 state->inlines_dirty[PIPE_SHADER_GEOMETRY] |= (stage_flags & VK_SHADER_STAGE_GEOMETRY_BIT) > 0;
2834 state->inlines_dirty[PIPE_SHADER_TESS_CTRL] |= (stage_flags & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) > 0;
2835 state->inlines_dirty[PIPE_SHADER_TESS_EVAL] |= (stage_flags & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) > 0;
2836 state->inlines_dirty[PIPE_SHADER_COMPUTE] |= (stage_flags & VK_SHADER_STAGE_COMPUTE_BIT) > 0;
2840 struct rendering_state *state);
2843 struct rendering_state *state)
2847 lvp_execute_cmd_buffer(secondary_buf, state);
2852 struct rendering_state *state)
2866 state->pctx->flush(state->pctx, NULL, 0);
2871 struct rendering_state *state)
2876 state->pctx->flush(state->pctx, NULL, 0);
2881 struct rendering_state *state)
2883 finish_fence(state);
2892 struct rendering_state *state)
2894 finish_fence(state);
2898 struct rendering_state *state)
2905 emit_compute_state(state);
2907 emit_state(state);
2911 pool->queries[qcmd->query] = state->pctx->create_query(state->pctx,
2915 state->pctx->begin_query(state->pctx, pool->queries[qcmd->query]);
2919 struct rendering_state *state)
2925 state->pctx->end_query(state->pctx, pool->queries[qcmd->query]);
2930 struct rendering_state *state)
2937 emit_compute_state(state);
2939 emit_state(state);
2943 pool->queries[qcmd->query] = state->pctx->create_query(state->pctx,
2947 state->pctx->begin_query(state->pctx, pool->queries[qcmd->query]);
2951 struct rendering_state *state)
2957 state->pctx->end_query(state->pctx, pool->queries[qcmd->query]);
2961 struct rendering_state *state)
2967 state->pctx->destroy_query(state->pctx, pool->queries[i]);
2974 struct rendering_state *state)
2979 pool->queries[qcmd->query] = state->pctx->create_query(state->pctx,
2984 state->pctx->flush(state->pctx, NULL, 0);
2985 state->pctx->end_query(state->pctx, pool->queries[qcmd->query]);
2990 struct rendering_state *state)
3008 state->pctx->get_query_result_resource(state->pctx,
3019 state->pctx->get_query_result_resource(state->pctx,
3027 state->pctx->get_query_result_resource(state->pctx,
3046 map = state->pctx->buffer_map(state->pctx,
3051 state->pctx->buffer_unmap(state->pctx, src_t);
3058 struct rendering_state *state)
3087 state->pctx->clear_texture(state->pctx, image->bo,
3094 struct rendering_state *state)
3118 surf = create_img_surface_bo(state, range,
3123 state->pctx->clear_depth_stencil(state->pctx,
3130 state->pctx->surface_destroy(state->pctx, surf);
3136 struct rendering_state *state)
3143 imgv = state->color_att[att->colorAttachment].imgv;
3145 imgv = state->ds_imgv;
3173 rect->rect.extent.width = MIN2(rect->rect.extent.width, state->framebuffer.width - rect->rect.offset.x);
3174 rect->rect.extent.height = MIN2(rect->rect.extent.height, state->framebuffer.height - rect->rect.offset.y);
3175 if (state->info.view_mask) {
3176 u_foreach_bit(i, state->info.view_mask)
3177 clear_attachment_layers(state, imgv, &rect->rect,
3182 clear_attachment_layers(state, imgv, &rect->rect,
3191 struct rendering_state *state)
3236 state->pctx->blit(state->pctx, &info);
3241 struct rendering_state *state, bool indexed)
3245 state->info.index_bounds_valid = false;
3246 state->info.index_size = state->index_size;
3247 state->info.index.resource = state->index_buffer;
3248 state->info.max_index = ~0;
3250 state->info.index_size = 0;
3251 state->indirect_info.offset = cmd->u.draw_indirect_count.offset;
3252 state->indirect_info.stride = cmd->u.draw_indirect_count.stride;
3253 state->indirect_info.draw_count = cmd->u.draw_indirect_count.max_draw_count;
3254 state->indirect_info.buffer = lvp_buffer_from_handle(cmd->u.draw_indirect_count.buffer)->bo;
3255 state->indirect_info.indirect_draw_count_offset = cmd->u.draw_indirect_count.count_buffer_offset;
3256 state->indirect_info.indirect_draw_count = lvp_buffer_from_handle(cmd->u.draw_indirect_count.count_buffer)->bo;
3258 state->pctx->set_patch_vertices(state->pctx, state->patch_vertices);
3259 state->pctx->draw_vbo(state->pctx, &state->info, 0, &state->indirect_info, &draw, 1);
3264 struct rendering_state *state)
3286 handle_descriptor(state, dyn_info, binding,
3373 struct rendering_state *state)
3383 handle_compute_push_descriptor_set(pds, &dyn_info, state);
3403 handle_descriptor(state, &dyn_info, binding,
3408 handle_descriptor(state, &dyn_info, binding,
3413 handle_descriptor(state, &dyn_info, binding,
3418 handle_descriptor(state, &dyn_info, binding,
3423 handle_descriptor(state, &dyn_info, binding,
3434 struct rendering_state *state)
3436 handle_push_descriptor_set_generic(&cmd->u.push_descriptor_set_khr, state);
3440 struct rendering_state *state)
3526 handle_push_descriptor_set_generic(pds, state);
3531 struct rendering_state *state)
3543 if (state->so_targets[idx])
3544 state->pctx->stream_output_target_destroy(state->pctx, state->so_targets[idx]);
3546 state->so_targets[idx] = state->pctx->create_stream_output_target(state->pctx,
3551 state->num_so_targets = btfb->first_binding + btfb->binding_count;
3555 struct rendering_state *state)
3566 pipe_buffer_read(state->pctx,
3572 state->pctx->set_stream_output_targets(state->pctx, state->num_so_targets,
3573 state->so_targets, offsets);
3577 struct rendering_state *state)
3587 offset = state->pctx->stream_output_target_offset(state->so_targets[i]);
3589 pipe_buffer_write(state->pctx,
3596 state->pctx->set_stream_output_targets(state->pctx, 0, NULL, NULL);
3600 struct rendering_state *state)
3605 pipe_buffer_read(state->pctx,
3610 state->info.start_instance = cmd->u.draw_indirect_byte_count_ext.first_instance;
3611 state->info.instance_count = cmd->u.draw_indirect_byte_count_ext.instance_count;
3612 state->info.index_size = 0;
3615 state->pctx->set_patch_vertices(state->pctx, state->patch_vertices);
3616 state->pctx->draw_vbo(state->pctx, &state->info, 0, &state->indirect_info, &draw, 1);
3620 struct rendering_state *state)
3623 state->pctx->render_condition_mem(state->pctx,
3629 static void handle_end_conditional_rendering(struct rendering_state *state)
3631 state->pctx->render_condition_mem(state->pctx, NULL, 0, false);
3635 struct rendering_state *state)
3653 state->velem.velems[location].src_offset = attrs[i].offset;
3654 state->velem.velems[location].vertex_buffer_index = attrs[i].binding;
3655 state->velem.velems[location].src_format = lvp_vk_format_to_pipe_format(attrs[i].format);
3656 state->vb[attrs[i].binding].stride = binding->stride;
3660 state->velem.velems[location].instance_divisor = 0;
3663 state->velem.velems[location].instance_divisor = d ? d : UINT32_MAX;
3673 state->velem.count = max_location + 1;
3674 state->vb_dirty = true;
3675 state->ve_dirty = true;
3679 struct rendering_state *state)
3681 state->rs_state.cull_face = vk_cull_to_pipe(cmd->u.set_cull_mode.cull_mode);
3682 state->rs_dirty = true;
3686 struct rendering_state *state)
3688 state->rs_state.front_ccw = (cmd->u.set_front_face.front_face == VK_FRONT_FACE_COUNTER_CLOCKWISE);
3689 state->rs_dirty = true;
3693 struct rendering_state *state)
3695 state->info.mode = vk_conv_topology(cmd->u.set_primitive_topology.primitive_topology);
3696 state->rs_dirty = true;
3701 struct rendering_state *state)
3703 state->dsa_dirty |= state->dsa_state.depth_enabled != cmd->u.set_depth_test_enable.depth_test_enable;
3704 state->dsa_state.depth_enabled = cmd->u.set_depth_test_enable.depth_test_enable;
3708 struct rendering_state *state)
3710 state->dsa_dirty |= state->dsa_state.depth_writemask != cmd->u.set_depth_write_enable.depth_write_enable;
3711 state->dsa_state.depth_writemask = cmd->u.set_depth_write_enable.depth_write_enable;
3715 struct rendering_state *state)
3717 state->dsa_dirty |= state->dsa_state.depth_func != cmd->u.set_depth_compare_op.depth_compare_op;
3718 state->dsa_state.depth_func = cmd->u.set_depth_compare_op.depth_compare_op;
3722 struct rendering_state *state)
3724 state->dsa_dirty |= state->dsa_state.depth_bounds_test != cmd->u.set_depth_bounds_test_enable.depth_bounds_test_enable;
3725 state->dsa_state.depth_bounds_test = cmd->u.set_depth_bounds_test_enable.depth_bounds_test_enable;
3729 struct rendering_state *state)
3731 state->dsa_dirty |= state->dsa_state.stencil[0].enabled != cmd->u.set_stencil_test_enable.stencil_test_enable ||
3732 state->dsa_state.stencil[1].enabled != cmd->u.set_stencil_test_enable.stencil_test_enable;
3733 state->dsa_state.stencil[0].enabled = cmd->u.set_stencil_test_enable.stencil_test_enable;
3734 state->dsa_state.stencil[1].enabled = cmd->u.set_stencil_test_enable.stencil_test_enable;
3738 struct rendering_state *state)
3741 state->dsa_state.stencil[0].func = cmd->u.set_stencil_op.compare_op;
3742 state->dsa_state.stencil[0].fail_op = vk_conv_stencil_op(cmd->u.set_stencil_op.fail_op);
3743 state->dsa_state.stencil[0].zpass_op = vk_conv_stencil_op(cmd->u.set_stencil_op.pass_op);
3744 state->dsa_state.stencil[0].zfail_op = vk_conv_stencil_op(cmd->u.set_stencil_op.depth_fail_op);
3748 state->dsa_state.stencil[1].func = cmd->u.set_stencil_op.compare_op;
3749 state->dsa_state.stencil[1].fail_op = vk_conv_stencil_op(cmd->u.set_stencil_op.fail_op);
3750 state->dsa_state.stencil[1].zpass_op = vk_conv_stencil_op(cmd->u.set_stencil_op.pass_op);
3751 state->dsa_state.stencil[1].zfail_op = vk_conv_stencil_op(cmd->u.set_stencil_op.depth_fail_op);
3753 state->dsa_dirty = true;
3757 struct rendering_state *state)
3759 state->rs_state.line_stipple_factor = cmd->u.set_line_stipple_ext.line_stipple_factor - 1;
3760 state->rs_state.line_stipple_pattern = cmd->u.set_line_stipple_ext.line_stipple_pattern;
3761 state->rs_dirty = true;
3765 struct rendering_state *state)
3767 state->rs_dirty |= state->depth_bias.enabled != cmd->u.set_depth_bias_enable.depth_bias_enable;
3768 state->depth_bias.enabled = cmd->u.set_depth_bias_enable.depth_bias_enable;
3772 struct rendering_state *state)
3775 state->rs_dirty |= state->blend_state.logicop_func != op;
3776 state->blend_state.logicop_func = op;
3780 struct rendering_state *state)
3782 state->patch_vertices = cmd->u.set_patch_control_points_ext.patch_control_points;
3786 struct rendering_state *state)
3788 state->info.primitive_restart = cmd->u.set_primitive_restart_enable.primitive_restart_enable;
3792 struct rendering_state *state)
3794 state->rs_dirty |= state->rs_state.rasterizer_discard != cmd->u.set_rasterizer_discard_enable.rasterizer_discard_enable;
3795 state->rs_state.rasterizer_discard = cmd->u.set_rasterizer_discard_enable.rasterizer_discard_enable;
3799 struct rendering_state *state)
3811 state->blend_dirty |= state->color_write_disables != disable_mask;
3812 state->color_write_disables = disable_mask;
3909 struct rendering_state *state)
3918 handle_pipeline(cmd, state);
3921 handle_set_viewport(cmd, state);
3924 handle_set_viewport_with_count(cmd, state);
3927 handle_set_scissor(cmd, state);
3930 handle_set_scissor_with_count(cmd, state);
3933 handle_set_line_width(cmd, state);
3936 handle_set_depth_bias(cmd, state);
3939 handle_set_blend_constants(cmd, state);
3942 handle_set_depth_bounds(cmd, state);
3945 handle_set_stencil_compare_mask(cmd, state);
3948 handle_set_stencil_write_mask(cmd, state);
3951 handle_set_stencil_reference(cmd, state);
3954 handle_descriptor_sets(cmd, state);
3957 handle_index_buffer(cmd, state);
3960 handle_vertex_buffers2(cmd, state);
3963 emit_state(state);
3964 handle_draw(cmd, state);
3967 emit_state(state);
3968 handle_draw_multi(cmd, state);
3971 emit_state(state);
3972 handle_draw_indexed(cmd, state);
3975 emit_state(state);
3976 handle_draw_indirect(cmd, state, false);
3979 emit_state(state);
3980 handle_draw_indirect(cmd, state, true);
3983 emit_state(state);
3984 handle_draw_multi_indexed(cmd, state);
3987 emit_compute_state(state);
3988 handle_dispatch(cmd, state);
3991 emit_compute_state(state);
3992 handle_dispatch_base(cmd, state);
3995 emit_compute_state(state);
3996 handle_dispatch_indirect(cmd, state);
3999 handle_copy_buffer(cmd, state);
4002 handle_copy_image(cmd, state);
4005 handle_blit_image(cmd, state);
4008 handle_copy_buffer_to_image(cmd, state);
4011 handle_copy_image_to_buffer2(cmd, state);
4014 handle_update_buffer(cmd, state);
4017 handle_fill_buffer(cmd, state);
4020 handle_clear_color_image(cmd, state);
4023 handle_clear_ds_image(cmd, state);
4026 handle_clear_attachments(cmd, state);
4029 handle_resolve_image(cmd, state);
4037 handle_pipeline_barrier(cmd, state);
4041 handle_begin_query_indexed_ext(cmd, state);
4044 handle_end_query_indexed_ext(cmd, state);
4047 handle_begin_query(cmd, state);
4050 handle_end_query(cmd, state);
4053 handle_reset_query_pool(cmd, state);
4056 handle_copy_query_pool_results(cmd, state);
4059 handle_push_constants(cmd, state);
4062 handle_execute_commands(cmd, state);
4065 emit_state(state);
4066 handle_draw_indirect_count(cmd, state, false);
4069 emit_state(state);
4070 handle_draw_indirect_count(cmd, state, true);
4073 handle_push_descriptor_set(cmd, state);
4076 handle_push_descriptor_set_with_template(cmd, state);
4079 handle_bind_transform_feedback_buffers(cmd, state);
4082 handle_begin_transform_feedback(cmd, state);
4085 handle_end_transform_feedback(cmd, state);
4088 emit_state(state);
4089 handle_draw_indirect_byte_count(cmd, state);
4092 handle_begin_conditional_rendering(cmd, state);
4095 handle_end_conditional_rendering(state);
4098 handle_set_vertex_input(cmd, state);
4101 handle_set_cull_mode(cmd, state);
4104 handle_set_front_face(cmd, state);
4107 handle_set_primitive_topology(cmd, state);
4110 handle_set_depth_test_enable(cmd, state);
4113 handle_set_depth_write_enable(cmd, state);
4116 handle_set_depth_compare_op(cmd, state);
4119 handle_set_depth_bounds_test_enable(cmd, state);
4122 handle_set_stencil_test_enable(cmd, state);
4125 handle_set_stencil_op(cmd, state);
4128 handle_set_line_stipple(cmd, state);
4131 handle_set_depth_bias_enable(cmd, state);
4134 handle_set_logic_op(cmd, state);
4137 handle_set_patch_control_points(cmd, state);
4140 handle_set_primitive_restart_enable(cmd, state);
4143 handle_set_rasterizer_discard_enable(cmd, state);
4146 handle_set_color_write_enable(cmd, state);
4149 handle_begin_rendering(cmd, state);
4152 handle_end_rendering(cmd, state);
4158 handle_event_reset2(cmd, state);
4161 handle_event_set2(cmd, state);
4164 handle_wait_events2(cmd, state);
4167 handle_write_timestamp2(cmd, state);
4183 struct rendering_state *state = queue->state;
4184 memset(state, 0, sizeof(*state));
4185 state->pctx = queue->ctx;
4186 state->uploader = queue->uploader;
4187 state->cso = queue->cso;
4188 state->blend_dirty = true;
4189 state->dsa_dirty = true;
4190 state->rs_dirty = true;
4191 state->vp_dirty = true;
4192 state->rs_state.point_tri_clip = true;
4193 state->rs_state.unclamped_fragment_depth_values = device->vk.enabled_extensions.EXT_depth_range_unrestricted;
4195 for (unsigned i = 0; i < ARRAY_SIZE(state->cso_ss_ptr[s]); i++)
4196 state->cso_ss_ptr[s][i] = &state->ss[s][i];
4199 lvp_execute_cmd_buffer(cmd_buffer, state);
4201 state->start_vb = -1;
4202 state->num_vb = 0;
4204 for (unsigned i = 0; i < ARRAY_SIZE(state->so_targets); i++) {
4205 if (state->so_targets[i]) {
4206 state->pctx->stream_output_target_destroy(state->pctx, state->so_targets[i]);
4211 for (unsigned i = 0; i < ARRAY_SIZE(state->sv[s]); i++) {
4212 if (state->sv[s][i])
4213 pipe_sampler_view_reference(&state->sv[s][i], NULL);
4218 i < ARRAY_SIZE(state->cso_ss_ptr[PIPE_SHADER_COMPUTE]); i++) {
4219 if (state->cso_ss_ptr[PIPE_SHADER_COMPUTE][i])
4220 state->pctx->delete_sampler_state(state->pctx, state->ss_cso[PIPE_SHADER_COMPUTE][i]);
4223 free(state->color_att);