Lines Matching defs:pipeline
185 struct lvp_pipeline *pipeline[2];
272 if (!state->pipeline[is_compute]->inlines[stage].can_inline)
274 struct lvp_pipeline *pipeline = state->pipeline[is_compute];
276 nir_shader *nir = nir_shader_clone(pipeline->pipeline_nir[stage], pipeline->pipeline_nir[stage]);
279 unsigned count = pipeline->inlines[stage].count[0];
283 unsigned offset = pipeline->inlines[stage].uniform_offsets[0][i];
298 NIR_PASS_V(nir, lvp_inline_uniforms, pipeline, inline_uniforms, 0);
302 u_foreach_bit(slot, pipeline->inlines[stage].can_inline) {
303 unsigned count = pipeline->inlines[stage].count[slot];
311 unsigned offset = pipeline->inlines[stage].uniform_offsets[slot][i];
315 NIR_PASS_V(nir, lvp_inline_uniforms, pipeline, inline_uniforms, slot);
322 !pipeline->inlines[stage].must_inline) {
324 pipeline->inlines[stage].can_inline = 0;
326 pipeline->shader_cso[sh] = lvp_pipeline_compile(pipeline, nir_shader_clone(NULL, pipeline->pipeline_nir[stage]));
327 shader_state = pipeline->shader_cso[sh];
329 shader_state = lvp_pipeline_compile(pipeline, nir);
553 LVP_FROM_HANDLE(lvp_pipeline, pipeline, cmd->u.bind_pipeline.pipeline);
555 if ((pipeline->layout->push_constant_stages & VK_SHADER_STAGE_COMPUTE_BIT) > 0)
556 state->has_pcbuf[PIPE_SHADER_COMPUTE] = pipeline->layout->push_constant_size > 0;
557 state->uniform_blocks[PIPE_SHADER_COMPUTE].count = pipeline->layout->stage[MESA_SHADER_COMPUTE].uniform_block_count;
558 for (unsigned j = 0; j < pipeline->layout->stage[MESA_SHADER_COMPUTE].uniform_block_count; j++)
559 state->uniform_blocks[PIPE_SHADER_COMPUTE].size[j] = pipeline->layout->stage[MESA_SHADER_COMPUTE].uniform_block_sizes[j];
560 if (!state->has_pcbuf[PIPE_SHADER_COMPUTE] && !pipeline->layout->stage[MESA_SHADER_COMPUTE].uniform_block_count)
564 (state->access[MESA_SHADER_COMPUTE].images_read != pipeline->access[MESA_SHADER_COMPUTE].images_read ||
565 state->access[MESA_SHADER_COMPUTE].images_written != pipeline->access[MESA_SHADER_COMPUTE].images_written);
567 state->access[MESA_SHADER_COMPUTE].buffers_written != pipeline->access[MESA_SHADER_COMPUTE].buffers_written;
568 memcpy(&state->access[MESA_SHADER_COMPUTE], &pipeline->access[MESA_SHADER_COMPUTE], sizeof(struct lvp_access_info));
570 state->dispatch_info.block[0] = pipeline->pipeline_nir[MESA_SHADER_COMPUTE]->info.workgroup_size[0];
571 state->dispatch_info.block[1] = pipeline->pipeline_nir[MESA_SHADER_COMPUTE]->info.workgroup_size[1];
572 state->dispatch_info.block[2] = pipeline->pipeline_nir[MESA_SHADER_COMPUTE]->info.workgroup_size[2];
573 state->inlines_dirty[PIPE_SHADER_COMPUTE] = pipeline->inlines[MESA_SHADER_COMPUTE].can_inline;
574 if (!pipeline->inlines[MESA_SHADER_COMPUTE].can_inline)
575 state->pctx->bind_compute_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_COMPUTE]);
614 LVP_FROM_HANDLE(lvp_pipeline, pipeline, cmd->u.bind_pipeline.pipeline);
615 const struct vk_graphics_pipeline_state *ps = &pipeline->graphics_state;
620 (state->access[sh].images_read != pipeline->access[sh].images_read ||
621 state->access[sh].images_written != pipeline->access[sh].images_written);
622 state->sb_dirty[sh] |= state->num_shader_buffers[sh] && state->access[sh].buffers_written != pipeline->access[sh].buffers_written;
624 memcpy(state->access, pipeline->access, sizeof(struct lvp_access_info) * 5); //4 vertex stages + fragment
631 state->uniform_blocks[sh].count = pipeline->layout->stage[i].uniform_block_count;
632 for (unsigned j = 0; j < pipeline->layout->stage[i].uniform_block_count; j++)
633 state->uniform_blocks[sh].size[j] = pipeline->layout->stage[i].uniform_block_sizes[j];
635 u_foreach_bit(stage, pipeline->layout->push_constant_stages) {
637 state->has_pcbuf[sh] = pipeline->layout->push_constant_size > 0;
651 u_foreach_bit(b, pipeline->graphics_state.shader_stages) {
655 state->inlines_dirty[PIPE_SHADER_FRAGMENT] = pipeline->inlines[MESA_SHADER_FRAGMENT].can_inline;
656 if (!pipeline->inlines[MESA_SHADER_FRAGMENT].can_inline)
657 state->pctx->bind_fs_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_FRAGMENT]);
661 state->inlines_dirty[PIPE_SHADER_VERTEX] = pipeline->inlines[MESA_SHADER_VERTEX].can_inline;
662 if (!pipeline->inlines[MESA_SHADER_VERTEX].can_inline)
663 state->pctx->bind_vs_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_VERTEX]);
667 state->inlines_dirty[PIPE_SHADER_GEOMETRY] = pipeline->inlines[MESA_SHADER_GEOMETRY].can_inline;
668 if (!pipeline->inlines[MESA_SHADER_GEOMETRY].can_inline)
669 state->pctx->bind_gs_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_GEOMETRY]);
670 state->gs_output_lines = pipeline->gs_output_lines ? GS_OUTPUT_LINES : GS_OUTPUT_NOT_LINES;
674 state->inlines_dirty[PIPE_SHADER_TESS_CTRL] = pipeline->inlines[MESA_SHADER_TESS_CTRL].can_inline;
675 if (!pipeline->inlines[MESA_SHADER_TESS_CTRL].can_inline)
676 state->pctx->bind_tcs_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_TESS_CTRL]);
680 state->inlines_dirty[PIPE_SHADER_TESS_EVAL] = pipeline->inlines[MESA_SHADER_TESS_EVAL].can_inline;
681 if (!pipeline->inlines[MESA_SHADER_TESS_EVAL].can_inline)
682 state->pctx->bind_tes_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_TESS_EVAL]);
694 state->pctx->bind_fs_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_FRAGMENT]);
710 state->rs_state.line_smooth = pipeline->line_smooth;
721 state->rs_state.line_rectangular = pipeline->line_rectangular;
857 state->disable_multisample = pipeline->disable_multisample;
876 if (pipeline->force_min_sample)
998 LVP_FROM_HANDLE(lvp_pipeline, pipeline, cmd->u.bind_pipeline.pipeline);
999 if (pipeline->is_compute_pipeline) {
1007 state->push_size[pipeline->is_compute_pipeline] = pipeline->layout->push_constant_size;
1008 state->pipeline[pipeline->is_compute_pipeline] = pipeline;