Lines Matching defs:access
133 struct lvp_access_info access[MESA_SHADER_STAGES];
381 state->sb[PIPE_SHADER_COMPUTE], state->access[MESA_SHADER_COMPUTE].buffers_written);
510 state->sb[sh], state->access[tgsi_processor_to_shader_stage(sh)].buffers_written);
564 (state->access[MESA_SHADER_COMPUTE].images_read != pipeline->access[MESA_SHADER_COMPUTE].images_read ||
565 state->access[MESA_SHADER_COMPUTE].images_written != pipeline->access[MESA_SHADER_COMPUTE].images_written);
567 state->access[MESA_SHADER_COMPUTE].buffers_written != pipeline->access[MESA_SHADER_COMPUTE].buffers_written;
568 memcpy(&state->access[MESA_SHADER_COMPUTE], &pipeline->access[MESA_SHADER_COMPUTE], sizeof(struct lvp_access_info));
620 (state->access[sh].images_read != pipeline->access[sh].images_read ||
621 state->access[sh].images_written != pipeline->access[sh].images_written);
622 state->sb_dirty[sh] |= state->num_shader_buffers[sh] && state->access[sh].buffers_written != pipeline->access[sh].buffers_written;
624 memcpy(state->access, pipeline->access, sizeof(struct lvp_access_info) * 5); //4 vertex stages + fragment
982 state->iv[pstage][i].access = 0;
985 u_foreach_bit(idx, state->access[stage].images_read) {
986 state->iv[pstage][idx].access |= PIPE_IMAGE_ACCESS_READ;
989 u_foreach_bit(idx, state->access[stage].images_written) {
990 state->iv[pstage][idx].access |= PIPE_IMAGE_ACCESS_WRITE;