Lines Matching defs:prog
93 struct zink_shader *zs, struct zink_gfx_program *prog,
109 if (zs->can_inline && (screen->is_cpu || prog->inlined_variant_count[pstage] < ZINK_MAX_INLINED_VARIANTS))
118 LIST_FOR_EACH_ENTRY_SAFE(iter, next, &prog->shader_cache[pstage][!!nonseamless_size][!!inline_size], list) {
136 mod = zink_shader_compile(screen, zs, prog->nir[stage], key);
163 zm->default_variant = !inline_size && list_is_empty(&prog->shader_cache[pstage][0][0]);
165 prog->inlined_variant_count[pstage]++;
167 list_add(&zm->list, &prog->shader_cache[pstage][!!nonseamless_size][!!inline_size]);
191 struct zink_gfx_program *prog, uint32_t mask,
196 bool first = !prog->modules[PIPE_SHADER_VERTEX];
197 uint32_t variant_hash = prog->last_variant_hash;
199 assert(prog->shaders[pstage]);
200 struct zink_shader_module *zm = get_shader_module_for_stage(ctx, screen, prog->shaders[pstage], prog, state);
202 if (prog->modules[pstage] == zm)
204 if (prog->modules[pstage])
205 variant_hash ^= prog->modules[pstage]->hash;
208 prog->modules[pstage] = zm;
209 variant_hash ^= prog->modules[pstage]->hash;
214 prog->last_variant_hash = prog->default_variant_hash;
216 prog->last_variant_hash = variant_hash;
218 p_atomic_dec(&prog->base.reference.count);
219 prog->default_variant_hash = prog->last_variant_hash;
283 zink_update_gfx_program(struct zink_context *ctx, struct zink_gfx_program *prog)
285 update_gfx_shader_modules(ctx, zink_screen(ctx->base.screen), prog, ctx->dirty_shader_stages & prog->stages_present, &ctx->gfx_pipeline_state);
404 assign_io(struct zink_gfx_program *prog, struct zink_shader *stages[ZINK_SHADER_COUNT])
418 if (!prog->nir[producer->info.stage])
419 prog->nir[producer->info.stage] = nir_shader_clone(prog, producer);
420 if (!prog->nir[j])
421 prog->nir[j] = nir_shader_clone(prog, consumer->nir);
422 zink_compiler_assign_io(prog->nir[producer->info.stage], prog->nir[j]);
435 struct zink_gfx_program *prog = rzalloc(NULL, struct zink_gfx_program);
436 if (!prog)
439 pipe_reference_init(&prog->base.reference, 1);
440 util_queue_fence_init(&prog->base.cache_fence);
443 list_inithead(&prog->shader_cache[i][0][0]);
444 list_inithead(&prog->shader_cache[i][0][1]);
445 list_inithead(&prog->shader_cache[i][1][0]);
446 list_inithead(&prog->shader_cache[i][1][1]);
448 prog->shaders[i] = stages[i];
449 prog->stages_present |= BITFIELD_BIT(i);
453 prog->shaders[PIPE_SHADER_TESS_EVAL]->generated =
454 prog->shaders[PIPE_SHADER_TESS_CTRL] =
456 prog->stages_present |= BITFIELD_BIT(PIPE_SHADER_TESS_CTRL);
459 assign_io(prog, prog->shaders);
462 prog->last_vertex_stage = stages[PIPE_SHADER_GEOMETRY];
464 prog->last_vertex_stage = stages[PIPE_SHADER_TESS_EVAL];
466 prog->last_vertex_stage = stages[PIPE_SHADER_VERTEX];
468 for (int i = 0; i < ARRAY_SIZE(prog->pipelines); ++i) {
469 _mesa_hash_table_init(&prog->pipelines[i], prog, NULL, equals_gfx_pipeline_state);
472 i == (prog->last_vertex_stage->nir->info.stage == MESA_SHADER_TESS_EVAL ? 4 : 3))
479 if (prog->shaders[i]) {
480 simple_mtx_lock(&prog->shaders[i]->lock);
481 _mesa_set_add(prog->shaders[i]->programs, prog);
482 simple_mtx_unlock(&prog->shaders[i]->lock);
483 zink_gfx_program_reference(ctx, NULL, prog);
484 _mesa_sha1_update(&sctx, prog->shaders[i]->base.sha1, sizeof(prog->shaders[i]->base.sha1));
487 _mesa_sha1_final(&sctx, prog->base.sha1);
489 if (!screen->descriptor_program_init(ctx, &prog->base))
492 zink_screen_get_pipeline_cache(screen, &prog->base);
493 return prog;
496 if (prog)
497 zink_destroy_gfx_program(ctx, prog);
665 struct zink_gfx_program *prog = (void*)pg;
667 if (prog->shaders[i])
668 num_bindings += get_num_bindings(prog->shaders[i], type);
684 struct zink_gfx_program *prog)
687 util_queue_fence_wait(&prog->base.cache_fence);
688 if (prog->base.layout)
689 VKSCR(DestroyPipelineLayout)(screen->dev, prog->base.layout, NULL);
692 if (prog->shaders[i]) {
693 _mesa_set_remove_key(prog->shaders[i]->programs, prog);
694 prog->shaders[i] = NULL;
696 destroy_shader_cache(screen, &prog->shader_cache[i][0][0]);
697 destroy_shader_cache(screen, &prog->shader_cache[i][0][1]);
698 destroy_shader_cache(screen, &prog->shader_cache[i][1][0]);
699 destroy_shader_cache(screen, &prog->shader_cache[i][1][1]);
700 ralloc_free(prog->nir[i]);
703 unsigned max_idx = ARRAY_SIZE(prog->pipelines);
706 if ((prog->stages_present &
716 hash_table_foreach(&prog->pipelines[i], entry) {
723 if (prog->base.pipeline_cache)
724 VKSCR(DestroyPipelineCache)(screen->dev, prog->base.pipeline_cache, NULL);
725 screen->descriptor_program_deinit(ctx, &prog->base);
727 ralloc_free(prog);
808 struct zink_gfx_program *prog,
819 assert(idx <= ARRAY_SIZE(prog->pipelines));
860 entry = _mesa_hash_table_search_pre_hashed(&prog->pipelines[idx], state->final_hash, state);
863 util_queue_fence_wait(&prog->base.cache_fence);
864 VkPipeline pipeline = zink_create_gfx_pipeline(screen, prog, state,
870 zink_screen_update_pipeline_cache(screen, &prog->base);
878 entry = _mesa_hash_table_insert_pre_hashed(&prog->pipelines[idx], state->final_hash, pc_entry, pc_entry);
1150 nir = zink_tgsi_to_nir(pctx->screen, shader->prog);
1152 nir = (struct nir_shader *)shader->prog;