Lines Matching defs:shader
443 sci.borderColor = VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK; // TODO with custom shader if we're super interested?
542 update_descriptor_state_ubo(struct zink_context *ctx, enum pipe_shader_type shader, unsigned slot, struct zink_resource *res)
547 ctx->di.descriptor_res[type][shader][slot] = res;
548 ctx->di.ubos[shader][slot].offset = ctx->ubos[shader][slot].buffer_offset;
550 ctx->di.ubos[shader][slot].buffer = res->obj->buffer;
551 ctx->di.ubos[shader][slot].range = ctx->ubos[shader][slot].buffer_size;
552 assert(ctx->di.ubos[shader][slot].range <= screen->info.props.limits.maxUniformBufferRange);
555 ctx->di.ubos[shader][slot].buffer = have_null_descriptors ? VK_NULL_HANDLE : null_buffer;
556 ctx->di.ubos[shader][slot].range = VK_WHOLE_SIZE;
560 ctx->di.push_valid |= BITFIELD64_BIT(shader);
562 ctx->di.push_valid &= ~BITFIELD64_BIT(shader);
568 update_descriptor_state_ssbo(struct zink_context *ctx, enum pipe_shader_type shader, unsigned slot, struct zink_resource *res)
573 ctx->di.descriptor_res[type][shader][slot] = res;
574 ctx->di.ssbos[shader][slot].offset = ctx->ssbos[shader][slot].buffer_offset;
576 ctx->di.ssbos[shader][slot].buffer = res->obj->buffer;
577 ctx->di.ssbos[shader][slot].range = ctx->ssbos[shader][slot].buffer_size;
580 ctx->di.ssbos[shader][slot].buffer = have_null_descriptors ? VK_NULL_HANDLE : null_buffer;
581 ctx->di.ssbos[shader][slot].range = VK_WHOLE_SIZE;
587 update_descriptor_state_sampler(struct zink_context *ctx, enum pipe_shader_type shader, unsigned slot, struct zink_resource *res)
592 ctx->di.descriptor_res[type][shader][slot] = res;
595 struct zink_buffer_view *bv = get_bufferview_for_binding(ctx, shader, type, slot);
596 ctx->di.tbos[shader][slot] = bv->buffer_view;
597 ctx->di.sampler_surfaces[shader][slot].bufferview = bv;
598 ctx->di.sampler_surfaces[shader][slot].is_buffer = true;
600 struct zink_surface *surface = get_imageview_for_binding(ctx, shader, type, slot);
601 ctx->di.textures[shader][slot].imageLayout = get_layout_for_binding(ctx, res, type, shader == PIPE_SHADER_COMPUTE);
602 ctx->di.textures[shader][slot].imageView = surface->image_view;
604 ctx->sampler_states[shader][slot] && ctx->sampler_states[shader][slot]->sampler_clamped) {
605 struct zink_sampler_state *state = ctx->sampler_states[shader][slot];
610 if (ctx->di.textures[shader][slot].sampler != sampler) {
611 screen->context_invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, slot, 1);
612 ctx->di.textures[shader][slot].sampler = sampler;
615 ctx->di.sampler_surfaces[shader][slot].surface = surface;
616 ctx->di.sampler_surfaces[shader][slot].is_buffer = false;
620 ctx->di.textures[shader][slot].imageView = VK_NULL_HANDLE;
621 ctx->di.textures[shader][slot].imageLayout = VK_IMAGE_LAYOUT_UNDEFINED;
622 ctx->di.tbos[shader][slot] = VK_NULL_HANDLE;
626 ctx->di.textures[shader][slot].imageView = null_surface->image_view;
627 ctx->di.textures[shader][slot].imageLayout = VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL;
628 ctx->di.tbos[shader][slot] = null_bufferview->buffer_view;
630 memset(&ctx->di.sampler_surfaces[shader][slot], 0, sizeof(ctx->di.sampler_surfaces[shader][slot]));
636 update_descriptor_state_image(struct zink_context *ctx, enum pipe_shader_type shader, unsigned slot, struct zink_resource *res)
641 ctx->di.descriptor_res[type][shader][slot] = res;
644 struct zink_buffer_view *bv = get_bufferview_for_binding(ctx, shader, type, slot);
645 ctx->di.texel_images[shader][slot] = bv->buffer_view;
646 ctx->di.image_surfaces[shader][slot].bufferview = bv;
647 ctx->di.image_surfaces[shader][slot].is_buffer = true;
649 struct zink_surface *surface = get_imageview_for_binding(ctx, shader, type, slot);
650 ctx->di.images[shader][slot].imageLayout = VK_IMAGE_LAYOUT_GENERAL;
651 ctx->di.images[shader][slot].imageView = surface->image_view;
652 ctx->di.image_surfaces[shader][slot].surface = surface;
653 ctx->di.image_surfaces[shader][slot].is_buffer = false;
657 memset(&ctx->di.images[shader][slot], 0, sizeof(ctx->di.images[shader][slot]));
658 ctx->di.texel_images[shader][slot] = VK_NULL_HANDLE;
662 ctx->di.images[shader][slot].imageView = null_surface->image_view;
663 ctx->di.images[shader][slot].imageLayout = VK_IMAGE_LAYOUT_GENERAL;
664 ctx->di.texel_images[shader][slot] = null_bufferview->buffer_view;
666 memset(&ctx->di.image_surfaces[shader][slot], 0, sizeof(ctx->di.image_surfaces[shader][slot]));
688 enum pipe_shader_type shader,
696 ctx->di.emulate_nonseamless[shader] &= ~mask;
699 if (ctx->sampler_states[shader][start_slot + i] != state)
700 zink_screen(pctx->screen)->context_invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, start_slot, 1);
702 if (ctx->sampler_states[shader][start_slot + i])
703 was_nonseamless = ctx->sampler_states[shader][start_slot + i]->emulate_nonseamless;
704 ctx->sampler_states[shader][start_slot + i] = state;
706 ctx->di.textures[shader][start_slot + i].sampler = state->sampler;
708 struct zink_surface *surface = get_imageview_for_binding(ctx, shader, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, start_slot + i);
712 ctx->di.textures[shader][start_slot + i].sampler = state->sampler_clamped;
719 ctx->di.emulate_nonseamless[shader] |= bit;
720 if (state->emulate_nonseamless != was_nonseamless && (ctx->di.cubes[shader] & bit)) {
721 struct zink_surface *surface = get_imageview_for_binding(ctx, shader, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, start_slot + i);
722 if (surface && ctx->di.image_surfaces[shader][start_slot + i].surface != surface) {
723 ctx->di.images[shader][start_slot + i].imageView = surface->image_view;
724 ctx->di.image_surfaces[shader][start_slot + i].surface = surface;
725 update_descriptor_state_sampler(ctx, shader, start_slot + i, zink_resource(surface->base.texture));
726 screen->context_invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, start_slot + i, 1);
730 ctx->di.textures[shader][start_slot + i].sampler = VK_NULL_HANDLE;
733 ctx->di.num_samplers[shader] = start_slot + num_samplers;
735 update_nonseamless_shader_key(ctx, shader);
1214 enum pipe_shader_type shader,
1218 const uint32_t bit = BITFIELD_BIT(shader);
1222 if (shader == PIPE_SHADER_COMPUTE) {
1225 key = &ctx->gfx_pipeline_state.shader_keys.key[shader];
1281 enum pipe_shader_type shader, uint index,
1288 struct zink_resource *res = zink_resource(ctx->ubos[shader][index].buffer);
1301 unbind_ubo(ctx, res, shader, index);
1302 new_res->ubo_bind_count[shader == PIPE_SHADER_COMPUTE]++;
1303 new_res->ubo_bind_mask[shader] |= BITFIELD_BIT(index);
1304 new_res->gfx_barrier |= zink_pipeline_flags_from_pipe_stage(shader);
1305 new_res->barrier_access[shader == PIPE_SHADER_COMPUTE] |= VK_ACCESS_UNIFORM_READ_BIT;
1306 update_res_bind_count(ctx, new_res, shader == PIPE_SHADER_COMPUTE, false);
1313 update |= ((index || zink_descriptor_mode == ZINK_DESCRIPTOR_MODE_LAZY) && ctx->ubos[shader][index].buffer_offset != offset) ||
1315 ctx->ubos[shader][index].buffer_size != cb->buffer_size;
1318 pipe_resource_reference(&ctx->ubos[shader][index].buffer, NULL);
1319 ctx->ubos[shader][index].buffer = buffer;
1321 pipe_resource_reference(&ctx->ubos[shader][index].buffer, buffer);
1323 ctx->ubos[shader][index].buffer_offset = offset;
1324 ctx->ubos[shader][index].buffer_size = cb->buffer_size;
1325 ctx->ubos[shader][index].user_buffer = NULL;
1330 if (index + 1 >= ctx->di.num_ubos[shader])
1331 ctx->di.num_ubos[shader] = index + 1;
1332 update_descriptor_state_ubo(ctx, shader, index, new_res);
1334 ctx->ubos[shader][index].buffer_offset = 0;
1335 ctx->ubos[shader][index].buffer_size = 0;
1336 ctx->ubos[shader][index].user_buffer = NULL;
1338 unbind_ubo(ctx, res, shader, index);
1339 update_descriptor_state_ubo(ctx, shader, index, NULL);
1341 update = !!ctx->ubos[shader][index].buffer;
1343 pipe_resource_reference(&ctx->ubos[shader][index].buffer, NULL);
1344 if (ctx->di.num_ubos[shader] == index + 1)
1345 ctx->di.num_ubos[shader]--;
1349 invalidate_inlined_uniforms(ctx, shader);
1353 zink_screen(pctx->screen)->context_invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_UBO, index, 1);
3219 /* if this is a non-shader barrier and there are binds, always queue a shader barrier */
3234 /* also queue a layout change if this is a non-shader layout */
3298 unreachable("unknown shader stage bit");
3810 rebind_ubo(struct zink_context *ctx, enum pipe_shader_type shader, unsigned slot)
3812 struct zink_resource *res = update_descriptor_state_ubo(ctx, shader, slot,
3813 ctx->di.descriptor_res[ZINK_DESCRIPTOR_TYPE_UBO][shader][slot]);
3814 zink_screen(ctx->base.screen)->context_invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_UBO, slot, 1);
3819 rebind_ssbo(struct zink_context *ctx, enum pipe_shader_type shader, unsigned slot)
3821 const struct pipe_shader_buffer *ssbo = &ctx->ssbos[shader][slot];
3827 update_descriptor_state_ssbo(ctx, shader, slot, res);
3828 zink_screen(ctx->base.screen)->context_invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_SSBO, slot, 1);
3833 rebind_tbo(struct zink_context *ctx, enum pipe_shader_type shader, unsigned slot)
3835 struct zink_sampler_view *sampler_view = zink_sampler_view(ctx->sampler_views[shader][slot]);
3845 update_descriptor_state_sampler(ctx, shader, slot, res);
3846 zink_screen(ctx->base.screen)->context_invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, slot, 1);
3851 rebind_ibo(struct zink_context *ctx, enum pipe_shader_type shader, unsigned slot)
3853 struct zink_image_view *image_view = &ctx->image_views[shader][slot];
3871 update_descriptor_state_image(ctx, shader, slot, res);
3872 zink_screen(ctx->base.screen)->context_invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_IMAGE, slot, 1);
3917 u_foreach_bit(shader, ubo_mask >> TC_BINDING_UBO_VS) {
3918 u_foreach_bit(slot, res->ubo_bind_mask[shader]) {
3919 if (&res->base.b != ctx->ubos[shader][slot].buffer) //wrong context
3921 rebind_ubo(ctx, shader, slot);
3932 u_foreach_bit(shader, ssbo_mask >> TC_BINDING_SSBO_VS) {
3933 u_foreach_bit(slot, res->ssbo_bind_mask[shader]) {
3934 struct pipe_shader_buffer *ssbo = &ctx->ssbos[shader][slot];
3937 rebind_ssbo(ctx, shader, slot);
3938 has_write |= (ctx->writable_ssbos[shader] & BITFIELD64_BIT(slot)) != 0;
3948 u_foreach_bit(shader, sampler_mask >> TC_BINDING_SAMPLERVIEW_VS) {
3949 u_foreach_bit(slot, res->sampler_binds[shader]) {
3950 struct zink_sampler_view *sampler_view = zink_sampler_view(ctx->sampler_views[shader][slot]);
3953 rebind_tbo(ctx, shader, slot);
3965 u_foreach_bit(shader, image_mask >> TC_BINDING_IMAGE_VS) {
3966 for (unsigned slot = 0; num_image_rebinds_remaining && slot < ctx->di.num_images[shader]; slot++) {
3967 struct zink_resource *cres = ctx->di.descriptor_res[ZINK_DESCRIPTOR_TYPE_IMAGE][shader][slot];
3971 rebind_ibo(ctx, shader, slot);
3972 const struct zink_image_view *image_view = &ctx->image_views[shader][slot];
4296 for (unsigned shader = PIPE_SHADER_VERTEX; shader < PIPE_SHADER_TYPES; shader++) {
4297 for (unsigned slot = 0; slot < ctx->di.num_ubos[shader]; slot++) {
4298 struct zink_resource *res = rebind_ubo(ctx, shader, slot);
4302 for (unsigned slot = 0; slot < ctx->di.num_sampler_views[shader]; slot++) {
4303 struct zink_resource *res = rebind_tbo(ctx, shader, slot);
4307 for (unsigned slot = 0; slot < ctx->di.num_ssbos[shader]; slot++) {
4308 struct zink_resource *res = rebind_ssbo(ctx, shader, slot);
4310 zink_batch_resource_usage_set(batch, res, (ctx->writable_ssbos[shader] & BITFIELD64_BIT(slot)) != 0);
4312 for (unsigned slot = 0; slot < ctx->di.num_images[shader]; slot++) {
4313 struct zink_resource *res = rebind_ibo(ctx, shader, slot);
4315 zink_batch_resource_usage_set(batch, res, (ctx->image_views[shader][slot].base.access & PIPE_IMAGE_ACCESS_WRITE) != 0);
4641 * a tess shader later