Lines Matching refs:screen
333 zink_screen_init_compiler(struct zink_screen *screen)
365 screen->nir_options = default_options;
367 if (!screen->info.feats.features.shaderInt64)
368 screen->nir_options.lower_int64_options = ~0;
370 if (!screen->info.feats.features.shaderFloat64) {
371 screen->nir_options.lower_doubles_options = ~0;
372 screen->nir_options.lower_flrp64 = true;
373 screen->nir_options.lower_ffma64 = true;
386 if (screen->info.driver_props.driverID == VK_DRIVER_ID_MESA_RADV ||
387 screen->info.driver_props.driverID == VK_DRIVER_ID_AMD_OPEN_SOURCE ||
388 screen->info.driver_props.driverID == VK_DRIVER_ID_AMD_PROPRIETARY)
389 screen->nir_options.lower_doubles_options = nir_lower_dmod;
402 zink_tgsi_to_nir(struct pipe_screen *screen, const struct tgsi_token *tokens)
410 return tgsi_to_nir(tokens, screen, false);
1047 struct zink_screen *screen = data;
1048 const bool has_int64 = screen->info.feats.features.shaderInt64;
1160 rewrite_bo_access(nir_shader *shader, struct zink_screen *screen)
1162 return nir_shader_instructions_pass(shader, rewrite_bo_access_instr, nir_metadata_dominance, screen);
1924 zink_shader_spirv_compile(struct zink_screen *screen, struct zink_shader *zs, struct spirv_shader *spirv)
2010 zs->nir->info.stage, "main", &spirv_options, &screen->nir_options);
2017 VkResult ret = VKSCR(CreateShaderModule)(screen->dev, &smci, NULL, &mod);
2018 bool success = zink_screen_handle_vkresult(screen, ret);
2057 zink_shader_compile(struct zink_screen *screen, struct zink_shader *zs, nir_shader *base_nir, const struct zink_shader_key *key)
2105 if (!zink_vs_key_base(key)->clip_halfz && screen->driver_workarounds.depth_clip_control_missing) {
2157 if (screen->driconf.inline_uniforms) {
2159 NIR_PASS_V(nir, rewrite_bo_access, screen);
2179 struct spirv_shader *spirv = nir_to_spirv(nir, sinfo, screen->spirv_version);
2181 mod = zink_shader_spirv_compile(screen, zs, spirv);
2674 struct zink_screen *screen = data;
2680 if (tex->is_sparse && screen->need_2D_sparse) {
2723 lower_1d_shadow(nir_shader *shader, struct zink_screen *screen)
2737 nir_shader_instructions_pass(shader, convert_1d_shadow_tex, nir_metadata_dominance, screen);
2742 scan_nir(struct zink_screen *screen, nir_shader *shader, struct zink_shader *zs)
2789 if (!screen->info.have_EXT_shader_atomic_float && !screen->is_cpu && !warned) {
3016 zink_shader_create(struct zink_screen *screen, struct nir_shader *nir,
3022 ret->sinfo.have_vulkan_memory_model = screen->info.have_KHR_vulkan_memory_model;
3055 if (screen->need_2D_zs)
3056 NIR_PASS_V(nir, lower_1d_shadow, screen);
3061 subgroup_options.subgroup_size = screen->info.props11.subgroupSize;
3065 if (!(screen->info.subgroup.supportedStages & mesa_to_vk_shader_stage(nir->info.stage))) {
3084 if (!screen->driconf.inline_uniforms) {
3086 NIR_PASS_V(nir, rewrite_bo_access, screen);
3097 bindless.bindless_set = screen->desc_set_id[ZINK_DESCRIPTOR_BINDLESS];
3112 scan_nir(screen, nir, ret);
3129 screen->compact_descriptors);
3142 var->data.descriptor_set = screen->desc_set_id[ztype];
3146 screen->compact_descriptors);
3165 var->data.descriptor_set = screen->desc_set_id[ztype];
3166 var->data.binding = zink_binding(nir->info.stage, vktype, var->data.driver_location, screen->compact_descriptors);
3183 if (!screen->info.feats.features.shaderInt64)
3218 struct zink_screen *screen = zink_screen(pscreen);
3233 if (!screen->info.feats.features.shaderImageGatherExtended)
3240 if (screen->driconf.inline_uniforms)
3293 zink_shader_tcs_compile(struct zink_screen *screen, struct zink_shader *zs, unsigned patch_vertices)
3298 return zink_shader_spirv_compile(screen, zs, NULL);
3323 zink_shader_tcs_create(struct zink_screen *screen, struct zink_shader *vs, unsigned vertices_per_patch)
3330 nir_shader *nir = nir_shader_create(NULL, MESA_SHADER_TESS_CTRL, &screen->nir_options, NULL);