Lines Matching refs:inst
235 struct tgsi_full_instruction inst = tgsi_default_full_instruction();
236 inst.Instruction.Opcode = TGSI_OPCODE_MOV;
237 inst.Instruction.NumDstRegs = 1;
238 inst.Dst[0].Register.File = TGSI_FILE_TEMPORARY,
239 inst.Dst[0].Register.Index = vtctx->input_temp[INPUT_TEMP_BLOCK_ID].temp;
240 inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZ;
241 inst.Instruction.NumSrcRegs = 1;
242 tgsi_transform_src_reg_xyzw(&inst.Src[0],
245 inst.Src[0].Register.SwizzleX = TGSI_SWIZZLE_X;
246 inst.Src[0].Register.SwizzleY = TGSI_SWIZZLE_Y;
247 inst.Src[0].Register.SwizzleZ = TGSI_SWIZZLE_Z;
248 inst.Src[0].Register.SwizzleW = TGSI_SWIZZLE_Z;
249 ctx->emit_instruction(ctx, &inst);
268 struct tgsi_full_instruction *inst)
272 (tgsi_opcode_infer_src_type(inst->Instruction.Opcode, 0) == TGSI_TYPE_DOUBLE ||
273 tgsi_opcode_infer_dst_type(inst->Instruction.Opcode, 0) == TGSI_TYPE_DOUBLE)) {
278 if (!vtctx->has_precise && inst->Instruction.Precise)
279 inst->Instruction.Precise = 0;
285 for (int i = 0; i < inst->Instruction.NumDstRegs; ++i) {
286 if (inst->Dst[i].Register.File == TGSI_FILE_TEMPORARY) {
287 uint32_t index = inst->Dst[i].Register.Index / 8;
288 uint32_t bits = inst->Dst[i].Register.WriteMask << (inst->Dst[i].Register.Index % 8);
298 if (inst->Instruction.Precise)
300 } else if (inst->Instruction.Opcode == TGSI_OPCODE_MOV) {
301 for (int i = 0; i < inst->Instruction.NumSrcRegs; ++i) {
302 if (inst->Src[i].Register.File == TGSI_FILE_TEMPORARY) {
303 uint32_t index = inst->Src[i].Register.Index / 8;
304 uint32_t read_mask = (1 << inst->Src[i].Register.SwizzleX) |
305 (1 << inst->Src[i].Register.SwizzleY) |
306 (1 << inst->Src[i].Register.SwizzleZ) |
307 (1 << inst->Src[i].Register.SwizzleW);
308 uint32_t bits = read_mask << (inst->Dst[i].Register.Index % 8);
310 inst->Instruction.Precise = 1;
324 if (tgsi_get_opcode_info(inst->Instruction.Opcode)->is_tex &&
325 inst->Src[0].Register.File == TGSI_FILE_IMMEDIATE) {
329 inst->Src[0].Register.File,
330 inst->Src[0].Register.Index);
331 inst->Src[0].Register.File = TGSI_FILE_TEMPORARY;
332 inst->Src[0].Register.Index = vtctx->src_temp;
335 for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
342 if (inst->Dst[i].Register.File == TGSI_FILE_OUTPUT) {
344 if (inst->Dst[i].Register.Index == vtctx->writemask_fixup_outs[j]) {
345 inst->Dst[i].Register.File = TGSI_FILE_TEMPORARY;
346 inst->Dst[i].Register.Index = vtctx->writemask_fixup_temps + j;
353 for (unsigned i = 0; i < inst->Instruction.NumSrcRegs; i++) {
354 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT &&
355 inst->Src[i].Register.Dimension &&
356 inst->Src[i].Dimension.Index == 0)
357 inst->Src[i].Register.Dimension = 0;
360 virgl_tgsi_rewrite_src_for_input_temp(&vtctx->input_temp[j], &inst->Src[i]);
365 if (tgsi_opcode_infer_src_type(inst->Instruction.Opcode, i) == TGSI_TYPE_DOUBLE) {
373 tgsi_transform_src_reg_xyzw(&temp_inst.Src[0], inst->Src[i].Register.File, inst->Src[i].Register.Index);
374 temp_inst.Src[0].Register.SwizzleX = inst->Src[i].Register.SwizzleX;
375 temp_inst.Src[0].Register.SwizzleY = inst->Src[i].Register.SwizzleY;
376 temp_inst.Src[0].Register.SwizzleZ = inst->Src[i].Register.SwizzleZ;
377 temp_inst.Src[0].Register.SwizzleW = inst->Src[i].Register.SwizzleW;
380 inst->Src[i].Register.File = TGSI_FILE_TEMPORARY;
381 inst->Src[i].Register.Index = vtctx->src_temp + i;
382 inst->Src[i].Register.SwizzleX = TGSI_SWIZZLE_X;
383 inst->Src[i].Register.SwizzleY = TGSI_SWIZZLE_Y;
384 inst->Src[i].Register.SwizzleZ = TGSI_SWIZZLE_Z;
385 inst->Src[i].Register.SwizzleW = TGSI_SWIZZLE_W;
391 if (inst->Instruction.Opcode != TGSI_OPCODE_MOV &&
392 !tgsi_get_opcode_info(inst->Instruction.Opcode)->is_tex &&
393 !tgsi_get_opcode_info(inst->Instruction.Opcode)->is_store &&
394 inst->Dst[0].Register.File == TGSI_FILE_OUTPUT &&
395 tgsi_opcode_infer_dst_type(inst->Instruction.Opcode, 0) != TGSI_TYPE_FLOAT) {
396 struct tgsi_full_instruction op_to_temp = *inst;
403 inst->Instruction.Opcode = TGSI_OPCODE_MOV;
404 inst->Instruction.NumSrcRegs = 1;
406 memset(&inst->Src[0], 0, sizeof(inst->Src[0]));
407 inst->Src[0].Register.File = TGSI_FILE_TEMPORARY;
408 inst->Src[0].Register.Index = vtctx->src_temp;
409 inst->Src[0].Register.SwizzleY = 1;
410 inst->Src[0].Register.SwizzleZ = 2;
411 inst->Src[0].Register.SwizzleW = 3;
414 ctx->emit_instruction(ctx, inst);
416 for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
418 inst->Dst[i].Register.File == TGSI_FILE_TEMPORARY &&
419 inst->Dst[i].Register.Index >= vtctx->writemask_fixup_temps &&
420 inst->Dst[i].Register.Index < vtctx->writemask_fixup_temps + vtctx->num_writemask_fixups) {
422 unsigned real_out = vtctx->writemask_fixup_outs[inst->Dst[i].Register.Index - vtctx->writemask_fixup_temps];
425 inst->Dst[i].Register.File, inst->Dst[i].Register.Index);